公开(公告)号：WO2012103367A3

公开(公告)日：2012-11-15

申请号：PCT/US2012022773

申请日：2012-01-26

Applicant: SOFT MACHINES INC ,  ABDALLAH MOHAMMAD

Inventor： ABDALLAH MOHAMMAD

IPC: G06F12/08 ,  G06F9/06 ,  G06F12/10

CPC classification number: G06F9/355 ,  G06F9/30054 ,  G06F9/30174 ,  G06F9/322 ,  G06F9/3802 ,  G06F9/4552 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1036 ,  G06F2212/604

Abstract: A method for managing mappings of storage on a code cache for a processor. The method includes storing a plurality of guest address to native address mappings as entries in a conversion look aside buffer, wherein the entries indicate guest addresses that have corresponding converted native addresses stored within a code cache memory, and receiving a subsequent request for a guest address at the conversion look aside buffer. The conversion look aside buffer is indexed to determine whether there exists an entry that corresponds to the index, wherein the index comprises a tag and an offset that is used to identify the entry that corresponds to the index. Upon a hit on the tag, the corresponding entry is accessed to retrieve a pointer to the code cache memory corresponding block of converted native instructions. The corresponding block of converted native instructions are fetched from the code cache memory for execution.

Abstract translation: 一种用于管理用于处理器的代码高速缓存上的存储的映射的方法。 该方法包括将多个访客地址存储到本地地址映射中作为转换旁边缓冲区中的条目，其中条目指示具有存储在代码高速缓冲存储器中的相应转换的本地地址的访客地址，以及接收对访客地址的后续请求 在转换看看缓冲区。 将缓冲器的转换看起来被索引以确定是否存在对应于索引的条目，其中索引包括用于标识对应于索引的条目的标签和偏移。 在标签上点击时，访问相应的条目以检索指向转换的本地指令的代码高速缓冲存储器相应块的指针。 转换的本地指令的相应块从代码高速缓冲存储器中取出以供执行。

公开(公告)号：WO2012135031A2

公开(公告)日：2012-10-04

申请号：PCT/US2012/030360

申请日：2012-03-23

Applicant: SOFT MACHINES, INC. ,  ABDALLAH, Mohammad

Inventor： ABDALLAH, Mohammad

IPC: G06F9/06 ,  G06F9/30 ,  G06F12/08 ,  G06F15/76

CPC classification number: G06F9/3009 ,  G06F9/30105 ,  G06F9/30123 ,  G06F9/34 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3851 ,  G06F9/5038 ,  G06F9/5077 ,  G06F2209/506 ,  Y02D10/22 ,  Y02D10/36

Abstract: A method for executing instructions using a plurality of virtual cores for a processor. The method includes receiving an incoming instruction sequence using a global front end scheduler, and partitioning the incoming instruction sequence into a plurality of code blocks of instructions. The method further includes generating a plurality of inheritance vectors describing interdependencies between instructions of the code blocks, and allocating the code blocks to a plurality of virtual cores of the processor, wherein each virtual core comprises a respective subset of resources of a plurality of partitionable engines. The code blocks are executed by using the partitionable engines in accordance with a virtual core mode and in accordance with the respective inheritance vectors.

Abstract translation: 一种用于使用用于处理器的多个虚拟核来执行指令的方法。 该方法包括使用全局前端调度器接收输入指令序列，并将输入指令序列划分成多个指令代码块。 所述方法还包括生成描述代码块的指令之间的相互依赖性并且将代码块分配给处理器的多个虚拟核心的多个继承向量，其中每个虚拟核心包括多个可分区引擎的相应资源子集 。 根据虚拟内核模式并根据各自的继承向量，通过使用可分区引擎执行代码块。

公开(公告)号：WO2012103245A2

公开(公告)日：2012-08-02

申请号：PCT/US2012022589

申请日：2012-01-25

Applicant: SOFT MACHINES INC ,  ABDALLAH MOHAMMAD

Inventor： ABDALLAH MOHAMMAD

IPC: G06F9/06 ,  G06F9/30 ,  G06F9/305

CPC classification number: G06F9/322 ,  G06F9/30058 ,  G06F9/30174 ,  G06F9/3808 ,  G06F9/3844 ,  G06F9/3863 ,  G06F9/4552

Abstract: A method for translating instructions for a processor. The method includes accessing a plurality of guest instructions that comprise multiple guest branch instructions comprising at least one guest far branch, and building an instruction sequence from the plurality of guest instructions by using branch prediction on the at least one guest far branch. The method further includes assembling a guest instruction block from the instruction sequence. The guest instruction block is translated to a corresponding native conversion block, wherein an at least one native far branch that corresponds to the at least one guest far branch and wherein the at least one native far branch includes an opposite guest address for an opposing branch path of the at least one guest far branch. Upon encountering a missprediction, a correct instruction sequence is obtained by accessing the opposite guest address.

Abstract translation: 翻译处理器指令的方法。 该方法包括访问包括包括至少一个访客远支路的多个访客支路指令的多个访客指令，并且通过在至少一个访客远支路上使用分支预测来从多个访客指令构建指令序列。 该方法还包括从指令序列中组装访客指令块。 访客指令块被翻译成对应的本地转换块，其中至少一个本地远端分支对应于至少一个远端分支，并且其中至少一个本地远端分支包括对于相反分支路径的对端地址 的至少一个客串远端分支。 在遇到错误预测时，通过访问相反的访客地址来获得正确的指令序列。

公开(公告)号：WO2012037491A2

公开(公告)日：2012-03-22

申请号：PCT/US2011/051992

申请日：2011-09-16

Applicant: SOFT MACHINES, INC. ,  ABDALLAH, Mohammad

Inventor： ABDALLAH, Mohammad

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30047 ,  G06F9/3804 ,  G06F9/3836 ,  G06F9/3844 ,  G06F9/3869 ,  G06F12/0875 ,  G06F2212/1016 ,  G06F2212/452

Abstract: A method of identifying instructions including accessing a plurality of instructions that comprise multiple branch instructions. For each branch instruction of the multiple branch instructions, a respective first mask is generated representing instructions that are executed if a branch is taken. A respective second mask is generated representing instructions that are executed if the branch is not taken. A prediction output is received that comprises a respective branch prediction for each branch instruction. For each branch instruction, the prediction output is used to select a respective resultant mask from among the respective first and second masks. For each branch instruction, a resultant mask of a subsequent branch is invalidated if a previous branch is predicted to branch over said subsequent branch. A logical operation is performed on all resultant masks to produce a final mask. The final mask is used to select a subset of instructions for execution.

Abstract translation: 一种识别指令的方法，包括访问包括多个分支指令的多个指令。 对于多个分支指令的每个分支指令，生成表示如果采用分支时执行的指令的相应的第一掩码。 生成相应的第二掩码，表示如果不采取分支则执行的指令。 接收包括每个分支指令的相应分支预测的预测输出。 对于每个分支指令，预测输出用于从相应的第一和第二掩模中选择相应的合成掩模。 对于每个分支指令，如果先前分支预测在所述后续分支上分支，则后续分支的合成掩码无效。 对所有得到的掩码执行逻辑运算以产生最终掩码。 最终的掩模用于选择要执行的指令子集。

公开(公告)号：WO2008061154A2

公开(公告)日：2008-05-22

申请号：PCT/US2007/084710

申请日：2007-11-14

Applicant: SOFT MACHINES, INC. ,  ABDALLAH, Mohammad

Inventor： ABDALLAH, Mohammad

IPC: G06F19/00

CPC classification number: G06F9/30123 ,  G06F9/30043 ,  G06F9/3009 ,  G06F9/30134 ,  G06F9/30138 ,  G06F9/3016 ,  G06F9/34 ,  G06F9/342 ,  G06F9/3808 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3851 ,  G06F9/3853 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/462 ,  G06F9/4843

Abstract: A unified architecture for dynamic generation, execution, synchronization and parallelization of complex instructions formats includes a virtual register file, register cache and register file hierarchy. A self-generating and synchronizing dynamic and static threading architecture provides efficient context switching.

Abstract translation: 用于复杂指令格式的动态生成，执行，同步和并行化的统一架构包括虚拟寄存器文件，寄存器高速缓存和寄存器文件层次结构。 自生产和同步动态和静态线程架构提供了有效的上下文切换。