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    HANDLING FALSELY DOOMED PARENTS OF NESTED TRANSACTIONS
    71.
    发明申请
    HANDLING FALSELY DOOMED PARENTS OF NESTED TRANSACTIONS 审中-公开
    处理虚假交易的父母

    公开(公告)号：WO2009002754A3

    公开(公告)日：2009-02-19

    申请号：PCT/US2008067145

    申请日：2008-06-16

    Applicant: MICROSOFT CORP

    Inventor： MAGRUDER MICHAEL M ,  DETLEFS DAVID ,  DUFFY JOHN JOSEPH ,  GRAEFE GOETZ ,  GROVER VINOD K

    IPC: G06F12/00

    CPC classification number: G06F17/30356 ,  G06F9/467 ,  G06F17/30362

    Abstract: [029] Various technologies and techniques are disclosed for detecting falsely doomed parent transactions of nested children in transactional memory systems. When rolling back nested transactions, a release count is tracked each time that a write lock is released due to rollback for a given nested transaction. For example, a write abort compensation map can be used to track the release count for each nested transaction. The number of times the nested transactions releases a write lock is recorded in their respective write abort compensation map. The release counts can be used during a validation of a parent transaction to determine if a failed optimistic read is really valid. If an aggregated release count for the nested children transactions accounts for the difference in version numbers exactly, then the optimistic read is valid.

    Abstract translation: 公开了各种技术和技术，用于检测事务存储器系统中嵌套子代的错误地注定的父事务。 当回滚嵌套事务时，每次释放写锁定是由于给定嵌套事务的回滚而被释放的。 例如，写入中止补偿映射可用于跟踪每个嵌套事务的发布计数。 嵌套事务释放写入锁定的次数记录在它们各自的写中止补偿映射中。 发布计数可以在验证父事务时使用，以确定失败的乐观读取是否真的有效。 如果嵌套子代交易的汇总发行计数正好说明了版本号的差异，则乐观读取有效。

    CACHE METADATA FOR IMPLEMENTING BOUNDED TRANSACTIONAL MEMORY
    72.
    发明申请
    CACHE METADATA FOR IMPLEMENTING BOUNDED TRANSACTIONAL MEMORY 审中-公开
    用于实现边界交易存储器的缓存元数据

    公开(公告)号：WO2008154191A2

    公开(公告)日：2008-12-18

    申请号：PCT/US2008/065376

    申请日：2008-05-30

    Applicant: MICROSOFT CORPORATION

    Inventor： GRAY, Jan ,  HARRIS, Timothy, L. ,  LARUS, James ,  SMITH, Burton

    IPC: G06F12/00

    CPC classification number: G06F9/467 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F12/0808 ,  G06F12/0842 ,  G06F2212/1016 ,  G06F2212/466 ,  G06F2212/507

    Abstract: Various technologies and techniques are disclosed for providing a bounded transactional memory application that accesses cache metadata in a cache of a central processing unit. When performing a transactional read from the bounded transactional memory application, a cache line metadata transaction-read bit is set. When performing a transactional write from the bounded transactional memory application, a cache line metadata transaction-write bit is set and a conditional store is performed. At commit time, if any lines marked with the transaction-read bit or the transaction-write bit were evicted or invalidated, all speculatively written lines are discarded. The application can also interrogate a cache line metadata eviction summary to determine whether a transaction is doomed and then take an appropriate action.

    Abstract translation: 公开了各种技术和技术，用于提供访问中央处理单元的高速缓存中的高速缓存元数据的有界事务存储器应用。 当从有界事务存储器应用程序执行事务读取时，设置缓存行元数据事务读取位。 当从有界事务存储器应用程序执行事务写入时，设置高速缓存行元数据事务写入位并执行条件存储。 在提交时，如果任何标有事务读取位或事务写入位的行被驱逐或无效，则所有推测写入的行都将被丢弃。 应用程序还可以询问高速缓存行元数据驱逐摘要以确定事务是否注定失败，然后采取适当的操作。

    DIRECT-UPDATE SOFTWARE TRANSACTIONAL MEMORY
    75.
    发明申请
    DIRECT-UPDATE SOFTWARE TRANSACTIONAL MEMORY 审中-公开
    直接更新软件交易记忆

    公开(公告)号：WO2007016302A2

    公开(公告)日：2007-02-08

    申请号：PCT/US2006029327

    申请日：2006-07-28

    Applicant: MICROSOFT CORP

    Inventor： HARRIS TIMOTHY L

    IPC: G06F13/00

    CPC classification number: G06F9/467 ,  Y10S707/99938 ,  Y10S707/99939

    Abstract: A transactional memory programming interface allows a thread to directly and safely access one or more shared memory locations within a transaction while maintaining control structures to manage memory accesses to those same locations by one or more other concurrent threads. Each memory location accessed by the thread is associated with an enlistment record, and each thread maintains a transaction log of its memory accesses. Within a transaction, a read operation is performed directly on the memory location, and a write operation is attempted directly on the memory location, as opposed to some intermediate buffer. The thread can detect inconsistencies between the enlistment record of a memory location and the thread's transaction log to determine whether the memory accesses within the transaction are not reliable and the transaction should be re-tried.

    Abstract translation: 事务存储器编程接口允许线程直接和安全地访问事务内的一个或多个共享存储器位置，同时维护控制结构以通过一个或多个其他并发线程来管理对那些相同位置的存储器访问。 由线程访问的每个内存位置都与一个登记记录相关联，每个线程都维护其内存访问的事务日志。 在事务中，直接对存储器位置执行读取操作，并且与一些中间缓冲器相反，直接在存储器位置上进行写入操作。 线程可以检测内存位置的登记记录与线程的事务日志之间的不一致，以确定事务中的内存访问是否不可靠，并且应重新尝试该事务。

    SELECTIVELY MONITORING LOADS TO SUPPORT SPECULATIVE PROGRAM EXECUTION
    76.
    发明申请
    SELECTIVELY MONITORING LOADS TO SUPPORT SPECULATIVE PROGRAM EXECUTION 审中-公开
    选择监测负荷来支持执行计划执行

    公开(公告)号：WO2004075045A3

    公开(公告)日：2005-08-11

    申请号：PCT/US2004003028

    申请日：2004-02-03

    Applicant: SUN MICROSYSTEMS INC ,  TREMBLAY MARC ,  JACOBSON QUINN A ,  CHAUDHRY SHAILDENDER

    Inventor： TREMBLAY MARC ,  JACOBSON QUINN A ,  CHAUDHRY SHAILDENDER

    IPC: G06F9/46 ,  G06F12/08 ,  G06F9/38

    CPC classification number: G06F12/0862 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/467 ,  G06F12/0815 ,  G06F12/0842

    Abstract: One embodiment of the present invention provides a system that selectively monitors load instructions to support transactional execution of a process, wherein changes made during the transactional execution are not committed to the architectural state of a processor until the transactional execution successfully completes. Upon encountering a load instruction during transactional execution of a block of instructions, the system determines whether the load instruction is a monitored load instruction or an unmonitored load instruction. If the load instruction is a monitored load instruction, the system performs the load operation, and load-marks a cache line associated with the load instruction to facilitate subsequent detection of an interfering data access to the cache line from another process. If the load instruction is an unmonitored load instruction, the system performs the load operation without load-marking the cache line.

    Abstract translation: 本发明的一个实施例提供了一种系统，其选择性地监视加载指令以支持进程的事务性执行，其中在事务执行期间进行的改变不被提交到处理器的体系结构状态，直到事务执行成功完成。 在执行指令块的事务执行期间遇到加载指令时，系统确定加载指令是监视加载指令还是不受监控的加载指令。 如果加载指令是被监视的加载指令，则系统执行加载操作，并加载标记与加载指令相关联的高速缓存行，以便随后检测到来自另一进程的高速缓存行的干扰数据访问。 如果加载指令是不受监控的加载指令，则系统将执行加载操作，而不加载标记缓存行。

    METHOD AND APPARATUS FOR DELAYING INTERFERING ACCESSES FROM OTHER THREADS DURING TRANSACTIONAL PROGRAM EXECUTION
    78.
    发明申请
    METHOD AND APPARATUS FOR DELAYING INTERFERING ACCESSES FROM OTHER THREADS DURING TRANSACTIONAL PROGRAM EXECUTION 审中-公开
    用于在交易程序执行期间延迟其他线程的干扰接入的方法和装置

    公开(公告)号：WO2004075052A1

    公开(公告)日：2004-09-02

    申请号：PCT/US2004/002685

    申请日：2004-01-30

    Applicant: SUN MICROSYSTEMS INC. ,  CHAUDHRY, Shaildender ,  TREMBLAY, Marc ,  JACOBSON, Quinn, A.

    Inventor： CHAUDHRY, Shaildender ,  TREMBLAY, Marc ,  JACOBSON, Quinn, A.

    IPC: G06F9/46

    CPC classification number: G06F12/0862 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30116 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/467 ,  G06F12/0815 ,  G06F12/0842

    Abstract: One embodiment of the present invention provides a system that facilitates delaying interfering memory accesses from other threads during transactional execution. During transactional execution of a block of instructions, the system receives a request from another thread (or processor) to perform a memory access involving a cache line. If performing the memory access on the cache line will interfere with the transactional execution and if it is possible to delay the memory access, the system delays the memory access and stores copy-back information for the cache line to enable the cache line to be copied back to the requesting thread. At a later time, when the memory access will no longer interfere with the transactional execution, the system performs the memory access and copies the cache line back to the requesting thread.

    Abstract translation: 本发明的一个实施例提供了一种在事务执行期间有助于延迟来自其他线程的干扰存储器访问的系统。 在一个指令块的事务执行期间，系统从另一个线程（或处理器）接收到执行涉及高速缓存线的存储器访问的请求。 如果执行高速缓存行上的存储器访问将干扰事务执行，并且如果可以延迟存储器访问，则系统延迟存储器访问并存储用于高速缓存行的复制信息以使得能够复制高速缓存行 回到请求线程。 在稍后的时间，当内存访问不再干扰事务执行时，系统执行内存访问并将缓存行复制回请求的线程。

    DEADLOCK DETECTION AND PREVENTION
    79.
    发明申请
    DEADLOCK DETECTION AND PREVENTION 审中-公开

    公开(公告)号：WO2019134747A1

    公开(公告)日：2019-07-11

    申请号：PCT/EP2018/050178

    申请日：2018-01-04

    Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  AVNI, Hillel

    Inventor： AVNI, Hillel

    IPC: G06F9/52 ,  G06F9/46

    CPC classification number: G06F9/524 ,  G06F9/467

    Abstract: An apparatus for preventing deadlocks during access to a data store includes a hardware processor which: detects that a lock required for performance of an incoming data store transaction is occupied; in response to detecting the lock is occupied, performs a hardware transactional memory (HTM) transaction on a data structure mapping dependencies amongst multiple data store transactions in order to determine if placing the incoming data store transaction in a waiting state creates a deadlock; and according to the determination, instructs the incoming data store transaction whether to wait for the lock to be freed or to abort.

    SYSTEM AND METHOD FOR MULTI-TILE DATA TRANSACTIONS IN A SYSTEM ON A CHIP
    80.
    发明申请
    SYSTEM AND METHOD FOR MULTI-TILE DATA TRANSACTIONS IN A SYSTEM ON A CHIP 审中-公开
    用于在芯片上的系统中进行多层数据交换的系统和方法

    公开(公告)号：WO2017139069A1

    公开(公告)日：2017-08-17

    申请号：PCT/US2017/013599

    申请日：2017-01-14

    Applicant: QUALCOMM INCORPORATED

    Inventor： GADELRAB, Serag ,  VARIA, Meghal ,  WURJANTARA, Wisnu ,  SUNG, Clara Ka Wah ,  STERNBERG, Mark ,  ANDRIJANIC, Vladan ,  RINALDI, Antonio ,  CHAMARTY, Vinod ,  SINHA, Pooja ,  WANG, Tao ,  GRUBER, Andrew

    IPC: G06F13/16

    CPC classification number: G06F9/467 ,  G06F13/1668 ,  G06F15/7807 ,  G06F17/30153 ,  G06F2212/401 ,  H03M7/30

    Abstract: Various embodiments of methods and systems for managing compressed data transaction sizes in a system on a chip ("SoC") in a portable computing device ("PCD") are disclosed. Based on lengths of compressed data tiles associated in a group, wherein the compressed data tiles are comprised within a compressed image file, multiple compressed data tiles may be aggregated into a single, multi-tile transaction. A metadata file may be generated in association with the single multi-tile transaction to identify the transaction as a multi-tile transaction and provide offset data to distinguish data associated with the compressed data tiles. Using the metadata, embodiments of the solution may provide for random access and modification of the compressed data stored in association with a multi-tile transaction.

    Abstract translation: 公开了用于管理便携式计算设备（“PCD”）中的片上系统（“SoC”）中的压缩数据事务大小的方法和系统的各种实施例。 基于组中关联的压缩数据瓦片的长度，其中压缩数据瓦片包含在压缩图像文件内，多个压缩数据瓦片可以被聚合成单个多瓦片事务。 元数据文件可以与单个多瓦片事务相关联地生成以将事务识别为多瓦片事务并且提供偏移数据以区分与压缩的数据瓦片相关联的数据。 使用元数据，解决方案的实施例可以提供对与多瓦片事务相关联地存储的压缩数据的随机访问和修改。

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