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公开(公告)号:WO2020179145A1
公开(公告)日:2020-09-10
申请号:PCT/JP2019/045371
申请日:2019-11-20
Applicant: パナソニックIPマネジメント株式会社
Inventor: 林 宙輝
Abstract: LBP特徴量をより速く生成可能なプロセッサを提供する。 プロセッサ(1)は、シフト処理(S2)、格納処理(S3)及び比較処理(S1)を1つの命令で実行する。シフト処理(S2)は、第3データ要素(DV31~DV34)を、第3ベクトルレジスタ(VR3)の所定領域(sm1~sm4)が空き領域になるようにシフトする。格納処理(S3)は、比較結果データ(HD1~HD4)を所定領域(sm1~sm4)に格納し、第3データ要素(DV31~DV34)を、所定領域(sm1~sm4)に格納された比較結果データ(HD1~HD4)を含むように更新する。比較処理(S1)は、第1データ要素(DV11~DV14)と、第2データ要素(DV21~DV24)とを大小比較して、比較結果(HD1~HD4)データを生成する。
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公开(公告)号:WO2020157535A1
公开(公告)日:2020-08-06
申请号:PCT/IB2019/000151
申请日:2019-02-01
Applicant: TOTAL SA
Inventor: HENON, Pascal
Abstract: A method for determining hydrocarbon production of a reservoir, comprising: modeling the reservoir with a gridded model having a coarse partition and a fine partition; determining a first matrix based on a Jacobian matrix function of the gridded model; determining (205) a first projector matrix as a concatenation of relevant generalized eigenvectors of a first square matrix and a second square matrix derived from the first matrix; extracting (602) a submatrix from the first projector matrix; determining (605) a projector matrix based on a concatenation of vectors derived from relevant generalized eigenvectors of a third square matrix and a fourth square matrix derived from said submatrix; determining a preconditioner operator based on the projector matrix; and determining hydrocarbon production for the reservoir based on the preconditioner operator.
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公开(公告)号:WO2020154907A1
公开(公告)日:2020-08-06
申请号:PCT/CN2019/073743
申请日:2019-01-29
Applicant: 深圳市科曼医疗设备有限公司
IPC: G06F17/16 , A61B5/0402
Abstract: 一种心电向量环的面积计算方法和装置,其中,心电向量环的面积计算方法包括获取待计算父环和待计算父环的起始点和终点(S101);基于起始点和终点按照递归算法判断待计算父环上是否存在结点(S102);如果待计算父环上存在结点,则根据结点划分待计算父环为至少两个无结点子环,以按照预设算法计算无结点子环的面积(S103),无结点子环为环上不存在结点的子环;将至少两个无结点子环的面积进行累加以得到待计算父环的面积(S104)。能够准确地计算8字形的心电向量环的面积。
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公开(公告)号:WO2020118555A1
公开(公告)日:2020-06-18
申请号:PCT/CN2018/120563
申请日:2018-12-12
Applicant: 深圳鲲云信息科技有限公司
Inventor: 徐欣
Abstract: 一种网络模型数据存取方法、装置及电子设备,所述方法包括:获取输入数据与配置参数,所述配置参数包括各网络层的配置参数(101);将所述输入数据及配置参数存入模拟存储器中,所述模拟存储器包括数组及数组索引(102);从所述模拟存储器中读取对应网络层的配置参数,根据所述配置参数配置对应网络层的计算引擎(103);将所述模拟存储器中的输入数据读取到所述计算引擎进行计算,得到计算结果(104);将所述计算结果存入所述模拟存储器中(105)。通过将输入数据及计算结果存入模拟存储器中,在模拟存储器中,通过索引到数组方式,可以提高数据读取的命中率,从而提高数据读取的速度,进而提高整个网络模型的数据处理速度。
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公开(公告)号:WO2020117926A1
公开(公告)日:2020-06-11
申请号:PCT/US2019/064454
申请日:2019-12-04
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor: NEMLEKAR, Milind N.
Abstract: A graphics processing unit (GPU) [100] schedules recurrent matrix multiplication operations at different subsets of CUs [110, 111, 112, 113] of the GPU. The GPU includes a scheduler [104] that receives sets of recurrent matrix multiplication operations [103, 114], such as multiplication operations associated with a recurrent neural network (RNN). The multiple operations associated with, for example, an RNN layer are fused into a single kernel, which is scheduled by the scheduler such that one work group is assigned per compute unit, thus assigning different ones of the recurrent matrix multiplication operations to different subsets of the CUs of the GPU. In addition, via software synchronization of the different workgroups, the GPU pipelines the assigned matrix multiplication operations so that each subset of CUs provides corresponding multiplication results to a different subset, and so that each subset of CUs executes at least a portion of the multiplication operations concurrently.
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公开(公告)号:WO2020116025A1
公开(公告)日:2020-06-11
申请号:PCT/JP2019/040150
申请日:2019-10-11
Applicant: 日本電気株式会社
Inventor: 増田 晃一
Abstract: コンパイル装置(10)のベクトルロード命令生成部(12)は、繰り返し計算処理にて要素a[i]として用いられる「第1データユニット群」をメモリから1ワード単位でパックした状態で第1ベクトルレジスタにロードする命令を生成する。各データユニットは、(1/2) k ワードである。ベクトルロード命令生成部(12)は、要素[i+2 k ]として用いられる第2データユニット群を第2ベクトルレジスタにロードする命令を生成する。ベクトルシフトダブル命令生成部(13)は、第1ベクトルレジスタ及び第2ベクトルレジスタのデータを一連のデータ列として(1/2) k ワード分シフトさせて得られたデータ列の一部を、1ワード単位でパックした状態で第3ベクトルレジスタにストアさせる命令を生成する。
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公开(公告)号:WO2020106502A1
公开(公告)日:2020-05-28
申请号:PCT/US2019/061052
申请日:2019-11-13
Applicant: MICROSOFT TECHNOLOGY LICENSING, LLC
Inventor: ZARAR, Shuayb M. , AMBARDEKAR, Amol Ashok , ZHANG, Jun
Abstract: A method of performing matrix computations includes receiving a compression-encoded matrix including a plurality of rows. Each row of the compression-encoded matrix has a plurality of defined element values and, for each such defined element value, a schedule tag indicating a schedule for using the defined element value in a scheduled matrix computation. The method further includes loading the plurality of rows of the compression-encoded matrix into a corresponding plurality of work memory banks, and providing decoded input data to a matrix computation module configured for performing the scheduled matrix computation. For each work memory bank, a next defined element value and a corresponding schedule tag are read. If the schedule tag meets a scheduling condition, the next defined element value is provided to the matrix computation module. Otherwise, a default element value is provided to the matrix computation module.
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公开(公告)号:WO2020094586A1
公开(公告)日:2020-05-14
申请号:PCT/EP2019/080136
申请日:2019-11-04
Applicant: MOVIDIUS LTD.
Inventor: CONNOR, Fergal , BERNARD, David , HANRAHAN, Niall
Abstract: Methods, apparatus, systems and articles of manufacture to perform dot product calculations using sparse vectors are disclosed. An example dot product calculator includes a counter to determine a trailing binary count of a control vector, the control vector corresponding to a first result of a first logic AND operation on a first bitmap of a first sparse vector and a second bitmap of a second sparse vector. The example dot product calculator further includes a mask generator to generate a mask vector based on the trailing binary count. The example dot product calculator further includes an interface to access a first value of the first sparse vector based on a second result of a second logic AND operation on the first bitmap and the mask vector and access a second value of the second sparse vector based on a third result of a third logic AND operation on the second bitmap and the mask vector. The example dot product calculator further includes a multiplier to multiply the first value with the second value to generate a product.
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80.
公开(公告)号:WO2020068323A1
公开(公告)日:2020-04-02
申请号:PCT/US2019/047774
申请日:2019-08-22
Applicant: INTEL CORPORATION
Inventor: SHARMA, Abhishek , KAVALIEROS, Jack T. , YOUNG, Ian A. , KRISHNAMURTHY, Ram , MANIPATRUNI, Sasikanth , AVCI, Uygar , CHEN, Gregory K. , MATHURIYA, Amrita , KUMAR, Raghavan , KNAG, Phil , SUMBUL, Huseyin Ekin , HARATIPOUR, Nazila , LE, Van H.
IPC: G06N3/063 , H01L27/108 , G11C11/409 , H01L27/11502 , G06N3/04 , G06F17/16 , H01L27/11
Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit. The CIM circuit includes a mathematical computation circuit having a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit. The CIM circuit includes a mathematical computation circuit having an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.
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