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    VERTICAL TUNNELING FIELD-EFFECT TRANSISTORS
    3.
    发明申请
    VERTICAL TUNNELING FIELD-EFFECT TRANSISTORS 审中-公开

    公开(公告)号：WO2019168519A1

    公开(公告)日：2019-09-06

    申请号：PCT/US2018/020188

    申请日：2018-02-28

    Applicant: INTEL CORPORATION

    Inventor： HUANG, Cheng-Ying ,  KAVALIEROS, Jack ,  YOUNG, Ian ,  METZ, Matthew ,  RACHMADY, Willy ,  AVCI, Uygar ,  AGRAWAL, Ashish ,  CHU-KUNG, Benjamin

    IPC: H01L29/73 ,  H01L29/732 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/10

    Abstract: Tunneling Field Effect Transistors (TFETs) are promising devices in that they promise significant performance increase and energy consumption decrease due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical fin-based TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates. In one embodiment, this can be different than the tunneling direction in the channel of later TFETs. In an embodiment, the disclosed vertical TFET can have a channel that includes the functionality of a drain. In an embodiment, the channel can be unintentionally doped (UID).

    VERTICAL TUNNELING FIELD-EFFECT TRANSISTORS
    6.
    发明申请
    VERTICAL TUNNELING FIELD-EFFECT TRANSISTORS 审中-公开

    公开(公告)号：WO2019168523A1

    公开(公告)日：2019-09-06

    申请号：PCT/US2018/020204

    申请日：2018-02-28

    Applicant: INTEL CORPORATION

    Inventor： HUANG, Cheng-Ying ,  KAVALIEROS, Jack ,  YOUNG, Ian ,  METZ, Matthew ,  RACHMADY, Willy ,  AVCI, Uygar ,  AGRAWAL, Ashish ,  CHU-KUNG, Benjamin

    IPC: H01L29/73 ,  H01L29/732 ,  H01L29/66 ,  H01L29/78

    Abstract: Tunneling Field Effect Transistors (TFETs) can offer significant performance increases and energy consumption decreases relative to traditional metal oxide semiconductor (MOS) transistors due to a steeper subthreshold slope (for example, smaller sub-threshold swing). In various embodiments, vertical TFETs can be fabricated in trenches, for example, silicon trenches. In another embodiment, vertical TFETs can be used on different material systems acting as a substrate and/or trenches (for example, Si, Ge, III-V semiconductors, GaN, and the like). In another embodiment, the channel can include a gradient layer. In an embodiment, the channel can include an indium(x) gallium(l-x) arsenide (InxGai-xAs) layer. In one embodiment, the tunneling direction in the channel of the vertical TFET can be perpendicular to the Si substrates.

    FIELD EFFECT TRANSISTOR STRUCTURES USING GERMANIUM NANOWIRES
    10.
    发明申请
    FIELD EFFECT TRANSISTOR STRUCTURES USING GERMANIUM NANOWIRES 审中-公开
    使用德国纳米颗粒的场效应晶体管结构

    公开(公告)号：WO2016105408A1

    公开(公告)日：2016-06-30

    申请号：PCT/US2014/072341

    申请日：2014-12-24

    Applicant: INTEL CORPORATION

    Inventor： KIM, Raseong ,  AVCI, Uygar ,  YOUNG, Ian

    IPC: H01L29/772

    CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L29/045 ,  H01L29/16 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

    Abstract: Field effect transistor structures are described that are formed using germanium nanowires. In one example, the structure has a germanium nanowire formed on a substrate along a predetermined confinement orientation, a first doped region of the nanowire at a first end of the nanowire to define a source, a second doped region of the nanowire at a second end of the nanowire to define a drain, and a gate dielectric formed over the nanowire between the source and the drain.

    Abstract translation: 描述了使用锗纳米线形成的场效应晶体管结构。 在一个示例中，该结构具有沿着预定限制取向在衬底上形成的锗纳米线，在纳米线的第一端处的纳米线的第一掺杂区域以限定源极，在第二端处形成纳米线的第二掺杂区域 的纳米线以限定漏极，以及形成在源极和漏极之间的纳米线上的栅极电介质。

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