公开(公告)号：WO2021194597A1

公开(公告)日：2021-09-30

申请号：PCT/US2020/066985

申请日：2020-12-23

Applicant: INTEL CORPORATION

Inventor： SHARMA, Abhishek ,  SATO, Noriyuki ,  ATANASOV, Sarah ,  SUMBUL, Huseyin Ekin ,  CHEN, Gregory K. ,  KNAG, Phil ,  KRISHNAMURTHY, Ram ,  YOO, Hui Jae ,  LE, Van H.

IPC: H01L27/108 ,  H01L27/12 ,  G11C11/4096 ,  G11C11/4085 ,  G11C11/4093 ,  G11C11/4097 ,  G11C2211/4066 ,  G11C5/025 ,  G11C7/1078 ,  H01L27/10844 ,  H01L27/1207 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1266 ,  H01L28/90

Abstract: Examples herein relate to a memory device comprising an eDRAM memory cell, the eDRAM memory cell can include a write circuit formed at least partially over a storage cell and a read circuit formed at least partially under the storage cell; a compute near memory device bonded to the memory device; a processor; and an interface from the memory device to the processor. In some examples, circuitry is included to provide an output of the memory device to emulate output read rate of an SRAM memory device comprises one or more of: a controller, a multiplexer, or a register. Bonding of a surface of the memory device can be made to a compute near memory device or other circuitry. In some examples, a layer with read circuitry can be bonded to a layer with storage cells. Any layers can be bonded together using techniques described herein.

公开(公告)号：WO2020068307A1

公开(公告)日：2020-04-02

申请号：PCT/US2019/047467

申请日：2019-08-21

Applicant: INTEL CORPORATION

Inventor： SUMBUL, Huseyin Ekin ,  KNAG, Phil ,  CHEN, Gregory K. ,  KUMAR, Raghavan ,  SHARMA, Abhishek ,  MANIPATRUNI, Sasikanth ,  MATHURIYA, Amrita ,  KRISHNAMURTHY, Ram ,  YOUNG, Ian A.

IPC: G06F7/544 ,  G11C8/10 ,  G06N3/08 ,  G11C8/08 ,  G11C7/12

Abstract: Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.

公开(公告)号：WO2020068323A1

公开(公告)日：2020-04-02

申请号：PCT/US2019/047774

申请日：2019-08-22

Applicant: INTEL CORPORATION

Inventor： SHARMA, Abhishek ,  KAVALIEROS, Jack T. ,  YOUNG, Ian A. ,  KRISHNAMURTHY, Ram ,  MANIPATRUNI, Sasikanth ,  AVCI, Uygar ,  CHEN, Gregory K. ,  MATHURIYA, Amrita ,  KUMAR, Raghavan ,  KNAG, Phil ,  SUMBUL, Huseyin Ekin ,  HARATIPOUR, Nazila ,  LE, Van H.

IPC: G06N3/063 ,  H01L27/108 ,  G11C11/409 ,  H01L27/11502 ,  G06N3/04 ,  G06F17/16 ,  H01L27/11

Abstract: An apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit. The CIM circuit includes a mathematical computation circuit coupled to a memory array. The memory array includes an embedded dynamic random access memory (eDRAM) memory array. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit. The CIM circuit includes a mathematical computation circuit having a switched capacitor circuit. The switched capacitor circuit includes a back-end-of-line (BEOL) capacitor coupled to a thin film transistor within the metal/dielectric layers of the semiconductor chip. Another apparatus is described. The apparatus includes a compute-in-memory (CIM) circuit. The CIM circuit includes a mathematical computation circuit having an accumulation circuit. The accumulation circuit includes a ferroelectric BEOL capacitor to store a value to be accumulated with other values stored by other ferroelectric BEOL capacitors.

公开(公告)号：WO2018057226A1

公开(公告)日：2018-03-29

申请号：PCT/US2017/048501

申请日：2017-08-24

Applicant: INTEL CORPORATION

Inventor： KUMAR, Raghavan ,  CHEN, Gregory K. ,  SUMBUL, Huseyin Ekin ,  KNAG, Phil

IPC: G06N3/063 ,  G06N3/08 ,  G11C11/54

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/088

Abstract: An integrated circuit (IC), as a computation block of a neuromorphic system, includes a time step controller to activate a time step update signal for performing a time-multiplexed selection of a group of neuromorphic states to update. The IC includes a first circuitry to, responsive to detecting the time step update signal for a selected group of neuromorphic states: generate an outgoing data signal in response to determining that a first membrane potential of the selected group of neuromorphic states exceeds a threshold value, wherein the outgoing data signal includes an identifier that identifies the selected group of neuromorphic states and a memory address (wherein the memory address corresponds to a location in a memory block associated with the integrated circuit), and update a state of the selected group of neuromorphic states in response to generation of the outgoing data signal.

Abstract translation: 作为神经形态系统的计算块的集成电路（IC）包括时间步长控制器，用于激活时间步长更新信号以执行时间多路复用选择一组神经形态状态到 更新。 所述IC包括第一电路，以响应于检测到所选神经形态组的时间步更新信号：响应于确定所选神经形态组的第一膜电位超过阈值而产生输出数据信号， 其中所述输出数据信号包括标识所选择的神经形态状态组的标识符和存储器地址（其中所述存储器地址对应于与所述集成电路相关联的存储器块中的位置），并且更新所选择的神经形态组的状态 响应于传出数据信号的产生状态。