公开(公告)号：WO2014085472A1

公开(公告)日：2014-06-05

申请号：PCT/US2013/072035

申请日：2013-11-26

Applicant: QUALCOMM INCORPORATED

Inventor： BROWN, Melinda J. ,  MORROW, Michael William ,  DIEFFENDERFER, James Norris ,  STEMPEL, Brian Michael ,  MCILVAINE, Michael Scott ,  SMITH, Rodney Wayne ,  SCHOTTMILLER, Jeffery M. ,  IRWIN, Andrew S

IPC: G06F9/30

CPC classification number: G06F9/3017 ,  G06F9/30167

Abstract: Fusing immediate value, write-based instructions in instruction processing circuits, and related processor systems, methods, and computer-readable media are disclosed. In one embodiment, a first instruction indicating an operation writing an immediate value to a register is detected by an instruction processing circuit. The circuit also detects at least one subsequent instruction indicating an operation that overwrites at least one first portion of the register while maintaining a value of a second portion of the register. The at least one subsequent instruction is converted (or replaced) with a fused instruction(s), which indicates an operation writing the at least one first portion and the second portion of the register. In this manner, conversion of multiple instructions for generating a constant into the fused instruction(s) removes the potential for a read-after-write hazard and associated consequences caused by dependencies between certain instructions, while reducing a number of clock cycles required to process the instructions.

Abstract translation: 公开了立即值的融合，指令处理电路中的基于写入的指令以及相关的处理器系统，方法和计算机可读介质。 在一个实施例中，指令处理电路检测指示向寄存器写入立即值的操作的第一指令。 电路还检测至少一个后续指令，指示在保持寄存器的第二部分的值的同时重写寄存器的至少一个第一部分的操作。 所述至少一个后续指令被转换（或替代）与一个融合指令，其指示写入寄存器的至少一个第一部分和第二部分的操作。 以这种方式，将用于产生常数的多个指令转换为融合指令消除了读写后危险和由特定指令之间的依赖性引起的相关后果的可能性，同时减少了处理所需的时钟周期数 说明。

公开(公告)号：WO2014062445A1

公开(公告)日：2014-04-24

申请号：PCT/US2013/064063

申请日：2013-10-09

Applicant: QUALCOMM INCORPORATED

Inventor： INGLE, Ajay Anant ,  HOFFMAN, Marc M. ,  MATHEW, Deepak

IPC: G06F9/30

CPC classification number: G06F9/30141 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30109 ,  G06F9/3012

Abstract: A method includes selectively coupling a first address line of a plurality of address lines and a second address line of the plurality of address lines to a first element bank of a plurality of element banks of a vector register file according to a selection pattern. The method also includes accessing data stored within the first element bank that is selectively addressed by the first address line via a single read port.

Abstract translation: 一种方法包括根据选择模式将多个地址线的第一地址线和多个地址线的第二地址线选择性地耦合到向量寄存器堆的多个元素组的第一元素组。 该方法还包括通过单个读取端口访问由第一地址线选择性寻址的存储在第一元素库内的数据。

公开(公告)号：WO2013184689A1

公开(公告)日：2013-12-12

申请号：PCT/US2013/044125

申请日：2013-06-04

Applicant: QUALCOMM INCORPORATED

Inventor： BROWN, Melinda, J. ,  DIEFFENDERFER, James, Norris ,  MORROW, Michael, W. ,  STEMPEL, Brian, Michael ,  MCILVAINE, Michael, Scott

IPC: G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/3826 ,  G06F9/3838 ,  G06F9/3885

Abstract: Issuing instructions to execution pipelines based on register-associated preferences and related instruction processing circuits, systems, methods, and computer-readable media are disclosed. In one embodiment, an instruction is detected in an instruction stream. Upon determining that the instruction specifies at least one source register, an execution pipeline preference(s) is determined based on at least one pipeline indicator associated with the at least one source register in a pipeline issuance table, and the instruction is issued to an execution pipeline based on the execution pipeline preference(s). Upon a determination that the instruction specifies at least one target register, at least one pipeline indicator associated with the at least one target register in the pipeline issuance table is updated based on the execution pipeline to which the instruction is issued. In this manner, optimal forwarding of instructions may be facilitated, thus improving processor performance.

Abstract translation: 公开了基于注册相关首选项和相关指令处理电路，系统，方法和计算机可读介质向执行管线发出指令。 在一个实施例中，在指令流中检测指令。 在确定指令指定至少一个源寄存器时，基于与流水线发行表中的至少一个源寄存器相关联的至少一个流水线指示符来确定执行管道偏好，并且该指令被发布到执行 基于执行管道偏好的流水线。 在确定指令指定至少一个目标寄存器时，基于发出指令的执行流水线更新与流水线发行表中的至少一个目标寄存器相关联的至少一个流水线指示符。 以这种方式，可以促进指令的最佳转发，从而提高处理器的性能。

公开(公告)号：WO2013181427A1

公开(公告)日：2013-12-05

申请号：PCT/US2013/043419

申请日：2013-05-30

Applicant: QUALCOMM INCORPORATED

Inventor： ZENG, Mao ,  PLONDKE, Erich James ,  CODRESCU, Lucian

IPC: G06K9/46

CPC classification number: G06K9/4638

Abstract: A method of determining whether a particular pixel of an image is a feature includes receiving data corresponding to a plurality of pixels (from the image) surrounding the particular pixel. The method further includes determining a set of comparison results, each corresponding to one of the plurality of pixels and indicating a result of comparing an attribute value corresponding to one of the plurality of pixels to a comparison value (based on a particular attribute value of the particular pixel and a threshold value). The method further includes performing a processor-executable instruction that, when executed by a processor, causes the processor to identify a subset of the set of comparison results that indicate the particular pixel is the feature. The identified subset may be a consecutive order of pixels of the plurality of pixels.

Abstract translation: 确定图像的特定像素是否是特征的方法包括接收与围绕该特定像素的多个像素（来自图像）相对应的数据。 所述方法还包括确定一组比较结果，每一个对应于所述多个像素之一并且指示将与所述多个像素中的一个相对应的属性值与比较值（基于所述多个像素的特定属性值）进行比较的结果 特定像素和阈值）。 所述方法还包括执行处理器可执行指令，所述指令在由处理器执行时使所述处理器识别所述特定像素是所述特征的所述一组比较结果的子集。 所识别的子集可以是多个像素的像素的连续顺序。

公开(公告)号：WO2013169836A1

公开(公告)日：2013-11-14

申请号：PCT/US2013/040040

申请日：2013-05-08

Applicant: QUALCOMM INCORPORATED

Inventor： KOOB, Christpher Edward ,  INGLE, Ajay Anant ,  CODRESCU, Lucian ,  VENKUMAHANTI, Suresh K.

IPC: G06F12/08

CPC classification number: G06F12/0842 ,  G06F12/0848 ,  G06F12/0864

Abstract: Systems and methods for allocation of cache lines in a shared partitioned cache (104) of a multi-threaded processor (102). A memory management unit (110) is configured to determine attributes associated with an address for a cache entry associated with a processing thread (T0) to be allocated in the cache. A configuration register (CP 300_0) is configured to store cache allocation information based on the determined attributes. A partitioning register (DP 310) is configured to store partitioning information for partitioning the cache into two or more portions (Main/Aux in FIG. 3). The cache entry is allocated into one of the portions of the cache based on the configuration register and the partitioning register.

Abstract translation: 用于在多线程处理器（102）的共享分区高速缓存（104）中分配高速缓存行的系统和方法。 存储器管理单元（110）被配置为确定与要在高速缓存中分配的处理线程（T0）相关联的高速缓存条目的地址相关联的属性。 配置寄存器（CP 300_0）被配置为基于所确定的属性来存储高速缓存分配信息。 分区寄存器（DP 310）被配置为存储用于将高速缓存分割成两个或更多个部分（图3中的主/辅助）的分区信息。 基于配置寄存器和分区寄存器，缓存条目被分配到高速缓存的一部分中。

公开(公告)号：WO2013158903A1

公开(公告)日：2013-10-24

申请号：PCT/US2013/037206

申请日：2013-04-18

Applicant: QUALCOMM INCORPORATED

Inventor： ZHOU, Bo ,  ZENG, Mao ,  DU, Junchen ,  CODRESCU, Lucian ,  JALIL, Suhail

IPC: H04N7/26 ,  H04N7/36

CPC classification number: H04N19/523 ,  H04N19/43 ,  H04N19/80

Abstract: A set of even interpolated sub-pixels is formed based on a pixel window and a tap coefficient register having a tap coefficient set, the pixel window is shifted and, applying the tap coefficient register a set of odd interpolated pixels is formed. The set of even interpolated sub-pixels and the set of odd interpolated sub-pixels are accumulated, repeatedly, until a termination condition is let. In the accumulating, the tap coefficient register is updated with another tap coefficient set, the pixel window is shifted, and the even interpolated pixels are incremented, the pixel window is then shifted again and the odd interpolated pixels are incremented.

Abstract translation: 基于像素窗口和具有抽头系数集合的抽头系数寄存器形成一组偶数内插子像素，像素窗口被移位，并且形成抽头系数寄存器一组奇插值像素。 偶数内插子像素组和奇数内插子像素组被重复累积，直到终止条件为let。 在累积中，抽头系数寄存器用另一个抽头系数组更新，像素窗口被移位，并且偶数内插像素递增，然后像素窗口再次移位，并且奇数内插像素增加。

公开(公告)号：WO2013149040A1

公开(公告)日：2013-10-03

申请号：PCT/US2013/034414

申请日：2013-03-28

Applicant: QUALCOMM INCORPORATED

Inventor： GE, Shaoping ,  CHAI, Chiaming ,  LILES, Stephen Edward ,  NGUYEN, Lam V. ,  FISCHER, Jeffrey Herbert

IPC: G06F1/04 ,  G11C7/22 ,  G11C11/419

CPC classification number: G06F1/04 ,  G11C7/222 ,  G11C11/417 ,  G11C11/418 ,  G11C11/419

Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit (100) includes a selective delay logic (102) to provide a programmable rising edge delay of the pulse clock (114), a selective pulse width widening logic (110) to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.

Abstract translation: 用于产生具有可编程边沿和脉冲宽度的脉冲时钟的系统和方法，其配置用于不同的存储器访问操作的需求。 脉冲时钟产生电路（100）包括提供脉冲时钟（114）的可编程上升沿延迟的选择延迟逻辑（102），选择脉冲宽度加宽逻辑（110），以提供脉冲时钟的可编程脉冲宽度 以及用于移位脉冲时钟的电压电平的内置电平移位器。 读操作的上升沿延迟被编程为对应于期望的读数组访问延迟，并且用于写操作的脉冲宽度被编程为比读操作的脉冲宽度宽。

公开(公告)号：WO2013123472A2

公开(公告)日：2013-08-22

申请号：PCT/US2013/026560

申请日：2013-02-17

Applicant: QUALCOMM INCORPORATED

Inventor： DOCKSER, Kenneth A. ,  LALL, Pathik Sunil

IPC: G06F7/485

CPC classification number: G06F7/485

Abstract: Provided are a floating-point adder and methods for implementing a floating-point adder with operand shifting based on a predicted exponent difference when performing an effective subtraction on normal or subnormal numbers. In an aspect, two least significant bits (LSBs) of a first floating-point operand's exponent are compared with two LSBs of a second floating-point operand's exponent to estimate a difference between the two exponents. A first shift of up to one of the first and the second operands is performed, based on the estimated difference. A prospective result is then produced by subtracting the first operand and the second operand. Contemporaneously, one of the first operand's exponent and the second operand's exponent is subtracted from the other of the first operand's exponent and the second operand's exponent to determine if the exponents actually differ by one or less. If the first operand's exponent and the second operand's exponent differ by one or less, the prospective result is provided as the raw difference of the operands.

Abstract translation: 提供了一种浮点加法器和用于在对正常或正常数进行有效减法时基于预测指数差来实现具有操作数移位的浮点加法器的方法。 在一个方面，将第一浮点运算数的指数的两个最低有效位（LSB）与第二浮点运算数的指数的两个LSB进行比较，以估计两个指数之间的差。 基于估计的差异，执行高达第一和第二操作数之一的第一移位。 然后通过减去第一操作数和第二操作数产生预期结果。 同时，第一个操作数的指数和第二个操作数的指数之一从第一个操作数的指数和第二个操作数的指数的另一个中减去，以确定指数实际上是否相差一个或更少。 如果第一个操作数的指数和第二个操作数的指数相差一个或多个，则预期结果作为操作数的原始差异提供。

公开(公告)号：WO2013109651A1

公开(公告)日：2013-07-25

申请号：PCT/US2013/021777

申请日：2013-01-16

Applicant: QUALCOMM INCORPORATED

Inventor： SASSONE, Peter, G. ,  MAMIDI, Suman ,  ABRAHAM, Elizabeth ,  VENKUMAHANTI, Suresh, K. ,  CODRESCU, Lucian

IPC: G06F9/30

CPC classification number: G06F9/30043 ,  G06F9/30047 ,  G06F9/3455 ,  G06F9/381 ,  G06F9/383

Abstract: Systems and methods for prefetching cache lines into a cache coupled to a processor. A hardware prefetcher is configured to recognize a memory access instruction as an autoincrement-address (AIA) memory access instruction, infer a stride value from an increment field of the AIA instruction, and prefetch lines into the cache based on the stride value. Additionally or alternatively, the hardware prefetcher is configured to recognize that prefetched cache lines are part of a hardware loop, determine a maximum loop count of the hardware loop, and a remaining loop count as a difference between the maximum loop count and a number of loop iterations that have been completed, select a number of cache lines to prefetch, and truncate an actual number of cache lines to prefetch to be less than or equal to the remaining loop count, when the remaining loop count is less than the selected number of cache lines.

Abstract translation: 将高速缓存线预取到耦合到处理器的高速缓存中的系统和方法。 硬件预取器被配置为将存储器访问指令识别为自动增量地址（AIA）存储器访问指令，从AIA指令的增量字段推断步幅值，并且基于步幅值将预取行预取到高速缓存中。 另外或替代地，硬件预取器被配置为识别预取的高速缓存行是硬件循环的一部分，确定硬件循环的最大循环计数，以及剩余循环计数作为最大循环计数和循环数之间的差 已经完成的迭代，当剩余循环数小于选定数量的缓存时，选择要预取的高速缓存行数，并将实际数量的缓存行预截取为小于或等于剩余循环计数 线。

公开(公告)号：WO2013082625A1

公开(公告)日：2013-06-06

申请号：PCT/US2012/067652

申请日：2012-12-03

Applicant: QUALCOMM INCORPORATED

Inventor： SARTORIUS, Thomas Andrew ,  SINGH, Subodh

IPC: G06F11/14

CPC classification number: G06F11/1441

Abstract: A processor reset control circuit is configured to automatically capture a prereset value of processor information stored in one or more hardware registers, as part of a reset operation state machine and prior to changing the processor information to its architecturally required post reset value. Such pre-reset processor information includes, for example one or more pre-reset values of the processor program counter (PC) and one or more pre-reset values of an operating-state mode register, both of which may be captured in one or more pre-reset capture storage devices which are then made available for evaluation purposes. Such pre-reset capture storage devices store pre-reset information in response to the reset and maintain the stored pre-reset information until another reset occurs.

Abstract translation: 处理器复位控制电路被配置为自动地捕获存储在一个或多个硬件寄存器中的处理器信息的预先存储值，作为复位操作状态机的一部分，并且在将处理器信息改变为其架构上所需的后置复位值之前。 这种预复位处理器信息包括例如处理器程序计数器（PC）的一个或多个预复位值和操作状态模式寄存器的一个或多个预复位值，它们都可以被捕获在一个或多个 更多的预复位捕获存储设备，然后可用于评估目的。 这种预复位捕获存储设备响应于重置来存储预复位信息，并保持所存储的预复位信息直到发生另一个复位。