公开(公告)号：WO2021040955A1

公开(公告)日：2021-03-04

申请号：PCT/US2020/044128

申请日：2020-07-30

Applicant: INTEL CORPORATION

Inventor： KAMGAING, Telesphor ,  DOGIAMIS, Georgios ,  EID, Feras ,  ALEKSOV, Aleksandar ,  SWAN, Johanna M.

IPC: H01L23/66 ,  H01L23/50 ,  H01L23/367 ,  H03H9/25 ,  H01L23/522

Abstract: Embodiments may relate to a radio frequency (RF) front-end module (FEM). The RF FEM may include an integrated die with an active portion and an acoustic wave resonator (AWR) portion adjacent to the active portion. The RF FEM may further include a lid coupled with the die. The lid may at least partially overlap the AWR portion at a surface of the die. Other embodiments may be described or claimed.

公开(公告)号：WO2019217025A1

公开(公告)日：2019-11-14

申请号：PCT/US2019/026904

申请日：2019-04-11

Applicant: INTEL IP CORPORATION

Inventor： THAI, Trang ,  DALMIA, Sidharth ,  SOVER, Raanan ,  HAGN, Josef ,  ASAF, Omer ,  SVENDSEN, Simon

IPC: H01Q9/04 ,  H01Q1/22

Abstract: Disclosed herein are antenna boards, antenna modules, and communication devices. For example, in some embodiments, an antenna board may include: an antenna feed substrate including an antenna feed structure, wherein the antenna feed substrate includes a ground plane, the antenna feed structure includes a first portion perpendicular to the ground plane and a second portion parallel to the ground plane, and the first portion is electrically coupled between the second portion and the first portion; and a millimeter wave antenna patch.

公开(公告)号：WO2019125500A1

公开(公告)日：2019-06-27

申请号：PCT/US2017/068370

申请日：2017-12-23

Applicant: INTEL CORPORATION

Inventor： GEORGE, Hubert C. ,  CLARKE, James S. ,  THOMAS, Nicole K. ,  PILLARISETTY, Ravi ,  YOSCOVITS, Zachary R. ,  CAUDILLO, Roman ,  ROBERTS, Jeanette M. ,  SINGH, Kanwaljit ,  MICHALAK, David J.

IPC: H01L29/778 ,  H01L29/66

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack including a quantum well layer; and a plurality of gates disposed above the quantum well stack; wherein the quantum well layer includes a two-dimensional material.

公开(公告)号：WO2019066843A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/053919

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： PILLARISETTY, Ravi ,  THOMAS, Nicole K. ,  SHARMA, Abhishek A. ,  GEORGE, Hubert C. ,  ROBERTS, Jeanette M. ,  YOSCOVITS, Zachary R. ,  CAUDILLO, Roman ,  SINGH, Kanwaljit ,  CLARKE, James S.

IPC: H01L29/778 ,  H01L29/15 ,  H01L29/66

Abstract: Disclosed herein are quantum dot devices and techniques. In some embodiments, a quantum computing processing device may include a quantum well stack, an array of quantum dot gate electrodes above the quantum well stack, and an associated array of selectors above the array of quantum dot gate electrodes. The array of quantum dot gate electrodes and the array of selectors may each be arranged in a grid.

公开(公告)号：WO2019066840A1

公开(公告)日：2019-04-04

申请号：PCT/US2017/053910

申请日：2017-09-28

Applicant: INTEL CORPORATION

Inventor： PILLARISETTY, Ravi ,  THOMAS, Nicole K. ,  GEORGE, Hubert C. ,  CAUDILLO, Roman ,  CLARKE, James S. ,  LE, Van H. ,  ROBERTS, Jeanette M. ,  AMIN, Payam ,  YOSCOVITS, Zachary R. ,  KOTLYAR, Roza ,  SINGH, Kanwaljit

IPC: G06N99/00 ,  B82Y10/00

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a (111) silicon substrate, a (111) germanium quantum well layer above the substrate, and a plurality of gates above the quantum well layer. In some embodiments, a quantum dot device may include a silicon substrate, an insulating material above the silicon substrate, a quantum well layer above the insulating material, and a plurality of gates above the quantum well layer.

公开(公告)号：WO2019059897A1

公开(公告)日：2019-03-28

申请号：PCT/US2017/052390

申请日：2017-09-20

Applicant: INTEL CORPORATION

Inventor： LIN, Kevin L. ,  MCKUBRE, Nicholas James Harold ,  THEN, Han Wui

IPC: H01F27/00 ,  H01L41/18 ,  H01F1/42

Abstract: Disclosed herein are inductor/core assemblies for integrated circuits (ICs), as well as related structures, methods, and devices. In some embodiments, an IC structure may include an inductor and a magnetic core in an interior of the inductor. The magnetic core may be movable perpendicular to a plane of the inductor.

公开(公告)号：WO2018236405A1

公开(公告)日：2018-12-27

申请号：PCT/US2017/039156

申请日：2017-06-24

Applicant: INTEL CORPORATION ,  TECHNISCHE UNIVERSITEIT DELFT

Inventor： SINGH, Kanwaljit ,  CLARKE, James S. ,  VELDHORST, Menno ,  VANDERSYPEN, Lieven Mark Koenraad

IPC: H01L29/12 ,  H01L29/06 ,  H01L29/66

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack; a plurality of first gate lines above the quantum well stack; a plurality of second gate lines above the quantum well stack, wherein the second gate lines are perpendicular to the first gate lines; and an array of regularly spaced magnet lines.

公开(公告)号：WO2018236404A1

公开(公告)日：2018-12-27

申请号：PCT/US2017/039155

申请日：2017-06-24

Applicant: INTEL CORPORATION ,  TECHNISCHE UNIVERSITEIT DELFT

Inventor： SINGH, Kanwaljit ,  CLARKE, James S. ,  VELDHORST, Menno ,  VANDERSYPEN, Lieven Mark Koenraad

IPC: H01L29/12 ,  H01L29/66 ,  H01L21/8234

Abstract: Quantum dot devices, and related systems and methods, are disclosed herein. In some embodiments, a quantum dot device may include a quantum well stack having a first face and a second opposing face; an array of parallel first gate lines at the first face or the second face of the quantum well stack; and an array of parallel second gate lines at the first face or the second face of the quantum well stack, wherein the second gate lines are oriented diagonal to the first gate lines.

公开(公告)号：WO2018200006A1

公开(公告)日：2018-11-01

申请号：PCT/US2017/030295

申请日：2017-04-29

Applicant: INTEL CORPORATION

Inventor： THOMAS, Nicole K. ,  PILLARISETTY, Ravi ,  CLARKE, James S. ,  GEORGE, Hubert C. ,  SINGH, Kanwaljit ,  YOSCOVITS, Zachary R. ,  CAUDILLO, Roman ,  ROBERTS, Jeanette M. ,  MICHALAK, David J.

IPC: H01L29/06 ,  H01L29/423 ,  H01L27/088

Abstract: Disclosed herein are quantum nanowire devices, and related methods and computing devices. In some embodiments, a quantum nanowire device may include: a first nanowire and a second nanowire arranged in a vertical array; a first gate at least partially wrapped around the first nanowire but not around the second nanowire; and a second gate at least partially wrapped around the second nanowire but not around the first nanowire, wherein the second gate is at least partially above the first gate.

公开(公告)号：WO2018118097A1

公开(公告)日：2018-06-28

申请号：PCT/US2016/068601

申请日：2016-12-24

Applicant: INTEL CORPORATION

Inventor： PILLARISETTY, Ravi ,  SHARMA, Abhishek A. ,  LE, Van H. ,  DEWEY, Gilbert W. ,  RACHMADY, Willy

IPC: H01L29/732 ,  H01L29/66 ,  H01L29/78

Abstract: Disclosed herein are vertical transistor devices and techniques. In some embodiments, a device may include: a semiconductor substrate; a first transistor in a first layer on the semiconductor substrate; and a second transistor in a second layer, wherein the second transistor includes a first source/drain (S/D) contact and a second S/D contact, the first layer is between the second layer and the semiconductor substrate, and the first S/D contact is between the second S/D contact and the first layer. In some embodiments, a device may include: a semiconductor substrate; and a transistor above the semiconductor substrate, wherein the transistor includes a channel and a source/drain (S/D) contact between the channel and the semiconductor substrate.