公开(公告)号：WO2023090920A1

公开(公告)日：2023-05-25

申请号：PCT/KR2022/018251

申请日：2022-11-17

申请人： 엘지이노텍 주식회사

发明人： 최병현

IPC分类号： H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00 ,  H01L25/16 ,  H01L23/64

摘要： 본 발명의 일 실시예에 따른 SiP 모듈은 기판; 상기 기판의 내부에 임베디드되는 제1IC(Integrated Chip); 상기 기판의 일면에 배치되는 제2IC를 포함하고, 상기 기판의 상기 일면과 타면을 관통하는 제1방향을 기준으로 상기 제1IC와 상기 제2IC는 적어도 일부가 오버랩되어 배치된다.

公开(公告)号：WO2023080456A1

公开(公告)日：2023-05-11

申请号：PCT/KR2022/014915

申请日：2022-10-04

申请人： 알에프머트리얼즈 주식회사

发明人： 한기우 ,  강원실 ,  정진영

IPC分类号： H01L23/66 ,  H01L23/498

摘要： 본 발명은 에어갭이 구비되는 패키지 구조에 관한 것으로 보다 상세하게는, 제1기판층; 상기 제1기판층의 상부에 구비되고 상부면 중앙에 소정의 패턴으로 신호선이 프린팅되며 상기 신호선의 일측과 타측에 각각 소정의 패턴으로 그라운드가 프린팅되는 제2기판층; 상기 신호선과 상기 그라운드의 상부에 구비되는 제3기판층; 상기 제3기판층의 상부에 구비되는 제4기판층;을 포함하되, 상기 제3기판층의 중앙에는 에어갭이 형성되고, 상기 에어갭의 상부는 상기 제4기판층의 하부 일측과 맞닿게 되고, 상기 에어갭의 하부는 상기 신호선과 맞닿는 것을 특징으로 한다.

公开(公告)号：WO2023070631A1

公开(公告)日：2023-05-04

申请号：PCT/CN2021/127779

申请日：2021-10-30

申请人： 上海华为技术有限公司

发明人： 丁文其 ,  周骞 ,  唐海正 ,  崔昌云 ,  梁乐 ,  郑文泉 ,  周小敏

IPC分类号： H04B1/04 ,  H04B7/06 ,  H01L23/66

摘要： 本申请实施例公开了一种通信芯片、通信模块、通信系统和基站，该通信芯片具体包括混频器、功分模块和开关模块，其中，混频器与第一接口连接，混频器用于对第一接口接收的第一输入信号或第一接口需要发送的第一输出信号进行变频处理；功分模块与第二接口连接，功分模块用于对第二接口接收的第二输入信号进行合路处理或对第二接口需要发送的第二输出信号进行功分处理；开关模块与第三接口连接，第三接口用于接收第三输入信号或发送第三输出信号，开关模块用于控制第二接口通过功分模块与第三接口通路，或通过功分模块和混频器与第一接口通路，使得该通信芯片可以作为驱动芯片或混频芯片同时串联使用，从而实现低成本减小功分器的损耗。

公开(公告)号：WO2023049142A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/044185

申请日：2022-09-21

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： TANG, Yiqi ,  MURUGAN, Rajen, Manicon

IPC分类号： H01L23/66 ,  H01L23/00 ,  H01L23/482

摘要： An electronic device (100) includes a die (108), a packages structure (120), and a multilevel redistribution structure (110) having a first via (111), a first level, a second via (113), a second level, and passivation material (119). The first level (111) has a conductive antenna (130), the first via (111) extends between the conductive antenna (130) and a conductive terminal (109) of the die (108), and the passivation material (119) extends between the first and second levels. The second via (113) extends through the passivation material (119) between the first and second levels. The second level has a conductive reflector (138).

公开(公告)号：WO2023048944A1

公开(公告)日：2023-03-30

申请号：PCT/US2022/042789

申请日：2022-09-07

申请人： QUALCOMM INCORPORATED

发明人： VEDULA, Ravi Pramod Kumar ,  SEKAR, Vikram

IPC分类号： H01L23/482 ,  H01L23/66 ,  H01L23/48

摘要： A dual-sided MOS IC includes an isolation layer and a MOS transistor. The isolation layer separates the MOS IC into a MOS IC frontside and a MOS IC backside. The MOS transistor is on both the MOS IC frontside and the MOS IC backside. The MOS transistor includes MOS gates, a first source connection in a first subsection of the MOS IC frontside, and a second source connection in a second subsection of the MOS IC backside. The first and second source connections are electrically coupled together through a first front-to-backside connection extending through the isolation layer. The MOS transistor further includes a first drain connection in the first subsection of the MOS IC backside, and a second drain connection in the second subsection of the MOS IC frontside. The first and second drain connections are electrically coupled together through a second front-to-backside connection extending through the isolation layer.

公开(公告)号：WO2023044193A1

公开(公告)日：2023-03-23

申请号：PCT/US2022/074363

申请日：2022-08-01

申请人： QUALCOMM INCORPORATED

发明人： WE, Hong Bok ,  BUOT, Joan Rey Villarba ,  PATIL, Aniket

IPC分类号： H01Q1/22 ,  H01L23/66 ,  H01Q21/06 ,  H01Q23/00 ,  H01Q25/00 ,  H01Q1/52 ,  H01Q21/28

摘要： Multi-sided antenna modules employing antennas on multiple sides of a package substrate for enhanced antenna coverage, and related antenna module fabrication methods. The multi-sided antenna module includes an integrated circuit (IC) die(s) disposed on a first side of the package substrate. The multi-sided antenna module further includes first and second substrate antenna layers disposed on respective first and second sides of the package substrate. The first substrate antenna layer includes a first antenna(s) disposed on the first side of the package substrate adjacent to the IC die(s). The second substrate antenna layer includes a second antenna(s) disposed on the second side of the package substrate opposite of the first side of the package substrate. In this manner, the multi-sided antenna module, including antennas on multiple sides of the package substrate, provides antenna coverage that extends from both sides of the package substrate to provide multiple directions of coverage.

公开(公告)号：WO2023031774A1

公开(公告)日：2023-03-09

申请号：PCT/IB2022/058095

申请日：2022-08-30

申请人： WUPATEC

发明人： BOUISSE, Gérard ,  DELAGE, Quentin ,  GONZALEZ, Julien ,  PLET, Sullivan

IPC分类号： H01L23/66 ,  H03F3/195 ,  H05K1/02 ,  H03F1/08 ,  H03F1/56 ,  H01L23/00 ,  H01L23/495

摘要： Circuit intégré d'amplificateur de puissance RF comprenant une puce à semi-conducteurs en boîtier, et carte de circuits imprimés le comprenant L'invention concerne un circuit intégré d'amplificateur de puissance RF (1) comprenant une puce à semi-conducteurs (2) encapsulée dans un boîtier (3), la puce (2) comprenant au moins un transistor de puissance RF (4) et un circuit de préadaptation d'entrée (5), le circuit de préadaptation d'entrée (5) comprenant une inductance shunt d'entrée et un réseau de stabilisation (16), l'inductance shunt d'entrée comprenant une ligne de transmission intégrée d'entrée (15a, 15b) et au moins un fil de connexion (14a, 14b), le réseau de stabilisation (16) comprenant au moins une résistance (17) et au moins un condensateur (18) reliés en parallèle entre la ligne de transmission intégrée d'entrée (15a, 15b) et la grille (4a) dudit au moins un transistor (4).

公开(公告)号：WO2023283295A1

公开(公告)日：2023-01-12

申请号：PCT/US2022/036300

申请日：2022-07-07

申请人： WOLFSPEED, INC.

发明人： JOO, Sung Chul ,  ANDRE, Ulf Hakan

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L23/66

摘要： A semiconductor device (10) comprises a lead (30), a board (50), and an electrically conductive layer (55) on the board (50). The lead (30) comprises a longitudinal axis (32) and is soldered to the electrically conductive layer (55). The semiconductor device (10) further comprises a first solder dam edge (95a) and a second solder dam edge (95b), each positioned on the lead (30) not more than 10 mils apart from each other along the longitudinal axis (32).

公开(公告)号：WO2022260887A1

公开(公告)日：2022-12-15

申请号：PCT/US2022/031541

申请日：2022-05-31

申请人： WOLFSPEED, INC.

发明人： WOO, Eng Wah ,  CHEANG, Samantha ,  KAM, Kok Meng ,  MABELL, Marvin ,  JANG, Haedong ,  KOMPOSCH, Alexander

IPC分类号： H01L23/66 ,  H01L23/538 ,  H01L21/58

摘要： A transistor package that includes a metal submount; a transistor die mounted on said metal submount; a surface mount IPD component that includes a dielectric substrate; and the dielectric substrate mounted on said metal submount. Additionally, the dielectric substrate includes one of the following: an irregular shape, a non-square shape, and a nonrectangular shape.

公开(公告)号：WO2022150348A1

公开(公告)日：2022-07-14

申请号：PCT/US2022/011261

申请日：2022-01-05

申请人： CREE, INC.

发明人： OREJOLA, Erwin ,  CONDIE, Brian ,  ANDRE, Ulf

IPC分类号： H01L23/49 ,  H01L23/66

摘要： A packaged semiconductor device includes a first bond pad (225), a second bond pad (165, 165'), a first bond wire that includes a first end bonded to the first bond pad (225) and a second end bonded to the second bond pad (165, 165'), and a second bond wire that includes a first end that is electrically connected to the first bond pad (225) and a second end that is electrically connected to the second bond pad (165, 165'). The first end of the second bond wire is bonded to the first end of the first bond wire. A method of bonding a bond wire includes bonding a first end of a first bond wire to a contact surface of a first bond pad (225) and bonding a first end of a second bond wire to a surface of the first end of the first bond wire.