公开(公告)号：WO2009055146A1

公开(公告)日：2009-04-30

申请号：PCT/US2008/074752

申请日：2008-08-29

Applicant: RAMBUS INC. ,  ABBASFAR, Aliazam

Inventor： ABBASFAR, Aliazam

IPC: H04L25/49 ,  H04L7/04

CPC classification number: H04L25/4908 ,  H04L7/041

Abstract: Embodiments of an encoder and a decoder are described. The encoder encodes data into a series of parallel codewords. Each codeword is expressed two sets of logic values (e.g., a set of logic 0s and a set of logic 1s) on two corresponding sets of output nodes, a first set and a second set. The encoder selects a current codeword such that it differs from the immediately preceding codeword by a fixed number of zero-to-one transitions on the first set of nodes and a fixed number of one-to-zero transitions on the second set of nodes. A decoder receives and decodes the codewords by comparing symbols on node pairs for which the symbols expressed in the prior code word were alike and decoding the results of those comparisons.

Abstract translation: 描述了编码器和解码器的实施例。 编码器将数据编码成一系列并行码字。 每个码字在两个对应的输出节点组，第一组和第二组上表示两组逻辑值（例如，一组逻辑0和一组逻辑1）。 编码器选择当前码字，使得其与紧接在前的码字不同，第一组节点上的固定数量的零到一个转换和第二组节点上的固定数量的一到零转换。 解码器通过比较在先前代码字中表示的符号相似的节点对上的符号并对这些比较的结果进行解码来接收和解码码字。

公开(公告)号：WO2009023302A3

公开(公告)日：2009-02-19

申请号：PCT/US2008/061846

申请日：2008-04-29

Applicant: RAMBUS INC. ,  ABBASFAR, Aliazam ,  ARYANFAR, Farshid

Inventor： ABBASFAR, Aliazam ,  ARYANFAR, Farshid

IPC: H04L27/20 ,  H04L27/22 ,  H04B7/04 ,  H04B7/06 ,  H04B7/08

Abstract: Embodiments of a circuit are described. In this circuit, a modulation circuit provides a first modulated electrical signal and a second modulated electrical signal, where a given modulated electrical signal, which can be either the first modulated electrical signal or the second modulated electrical signal, includes minimum-shift keying (MSK) modulated data. Moreover, a first phase-adjustment element, which is coupled to the modulation circuit, sets a relative phase between the first modulated electrical signal and the second modulated electrical signal based on a phase value of the first phase-adjustment element. Additionally, an output interface, which is coupled to the first phase-adjustment element, is coupled to one or more antenna elements which output signals. These signals include a quadrature phase-shift-keying (QPSK) signal corresponding to the first modulated electrical signal and the second modulated electrical signal.

公开(公告)号：WO2008144151A3

公开(公告)日：2009-01-15

申请号：PCT/US2008061117

申请日：2008-04-22

Applicant: RAMBUS INC ,  ABBASFAR ALIAZAM ,  KOMIJANI ABBAS

Inventor： ABBASFAR ALIAZAM ,  KOMIJANI ABBAS

IPC: H04L27/26 ,  H04B7/06

CPC classification number: H04B7/06 ,  H04L27/2614 ,  H04L27/2628

Abstract: Embodiments of a communication circuit are described. This communication circuit includes an input node (212) to receive a set of data symbols and a partitioner (216) coupled to the input node. The partitioner is to divide the set of data symbols into M irregular subgroups of data symbols, a given one of which includes non-consecutive data symbols in the set of data symbols. Moreover, this given irregular subgroup of data symbols includes at least two pairs ofadjacent data symbols having different inter-data-symbol spacings in the set of data symbols. This communication circuit also includes M modulators (218-1,,218-Nl) coupled to the partitioner, where the given irregular subgroup of data symbols is coupled to a given modulator in the M modulators. Furthermore, the communication circuit includes M output nodes, where a given output node in the M output nodes is coupled to the given modulator and is to couple to an antenna element in M antenna elements (226).

Abstract translation: 描述通信电路的实施例。 该通信电路包括用于接收一组数据符号的输入节点（212）和耦合到输入节点的分割器（216）。 分割器将数据符号组分成M个不规则的数据符号子组，给定的一个数据符号包括数据符号组中的非连续数据符号。 此外，该给定的不规则数据符号子组包括在该组数据符号中具有不同的数据间符号间隔的至少两对相邻的数据符号。 该通信电路还包括耦合到分割器的M个调制器（218-1，...，218-N1），其中给定的不规则子数据符号耦合到M个调制器中的给定调制器。 此外，通信电路包括M个输出节点，其中M个输出节点中的给定输出节点耦合到给定的调制器，并且耦合到M个天线元件（226）中的天线元件。

公开(公告)号：WO2007145836A3

公开(公告)日：2008-12-18

申请号：PCT/US2007012815

申请日：2007-05-31

Applicant: JAALAA INC ,  MORRIS MARTIN ,  ANANDAKUMAR ANAND ,  ABBASFAR ALIAZAM

Inventor： MORRIS MARTIN ,  ANANDAKUMAR ANAND ,  ABBASFAR ALIAZAM

IPC: G08B13/14 ,  G06F17/00 ,  G08B5/22

CPC classification number: G07G1/0045 ,  G07G1/009 ,  H04L1/1867 ,  H04W4/12 ,  H04W52/0216 ,  H04W52/0219 ,  Y02D70/00 ,  Y02D70/166

Abstract: An implementation of a signaling protocol for low power and large scale wireless networks provides a media access control (MAC) that produces a low rate two-way communication link between a commercial infrastructure and a very large number of small, low-cost devices known as electronic tags. The numerous tags attached to merchandise or shelves communicate with a number of access points (AP) distributed throughout a facility containing merchandise for sale or storage. A store controller maintains the pricing database for the point of sale (POS) registers of the facility. Price changes are transmitted in real time to the tag, thus updating the merchandise tags and the point of sales (POS) registers simultaneously. The tags contain a controller and a battery in which conservation of power is crucial to the life of the tags.

Abstract translation: 用于低功率和大规模无线网络的信令协议的实现提供了媒体接入控制（MAC），其在商业基础设施和大量小型，低成本设备之间产生低速率双向通信链路，称为 电子标签。 连接到商品或货架上的许多标签与分发在包含销售或存储商品的设施的多个接入点（AP）通信。 商店控制器维护设施的销售点（POS）寄存器的定价数据库。 价格变化实时传输到标签，从而同时更新商品标签和销售点（POS）寄存器。 标签包含控制器和电池，其中电力守恒对于标签的寿命至关重要。

公开(公告)号：WO2012033664A4

公开(公告)日：2012-08-23

申请号：PCT/US2011049586

申请日：2011-08-29

Applicant: RAMBUS INC ,  KAVIANI KAMBIZ ,  AMIRKHANY AMIR ,  ABBASFAR ALIAZAM

Inventor： KAVIANI KAMBIZ ,  AMIRKHANY AMIR ,  ABBASFAR ALIAZAM

IPC: H03K19/0175 ,  G06F13/00

CPC classification number: H03K19/018585 ,  G06F13/4077

Abstract: Described are integrated signal interfaces that include receive amplifiers and termination elements. Termination control circuitry calibrates the impedances through the termination elements to take into account the transconductance of the receive amplifiers. Transconductance bias circuitry can be used to bias the receive amplifiers, and the bias can be derived from a reference voltage. The interfaces can derive the common-mode voltage from received signals as the reference voltage, rather than from a dedicated voltage reference.

Abstract translation: 描述了包括接收放大器和终端元件的集成信号接口。 终端控制电路通过端接元件校准阻抗，以考虑接收放大器的跨导。 可以使用跨导偏置电路来偏置接收放大器，偏置可以从参考电压中导出。 这些接口可以从接收到的信号中导出共模电压作为参考电压，而不是从专用参考电压中获得。

公开(公告)号：WO2011119359A2

公开(公告)日：2011-09-29

申请号：PCT/US2011/028295

申请日：2011-03-14

Applicant: RAMBUS INC. ,  AMIRKHANY, Amir ,  ABBASFAR, Aliazam ,  KAVIANI, Kambiz ,  BEYENE, Wendemagegnehu ,  WERNER, Carl, W.

Inventor： AMIRKHANY, Amir ,  ABBASFAR, Aliazam ,  KAVIANI, Kambiz ,  BEYENE, Wendemagegnehu ,  WERNER, Carl, W.

IPC: G11C7/10

CPC classification number: G11C7/1006 ,  G11C7/02

Abstract: Encoder and decoder circuits that encode and decode a series of data words to/from a series of code words. The data words include L symbols. The code words include M symbols, where M is larger than L. A set of tightly coupled M links to convey respective symbols in each of the series of code words. The code words are selected such that between every two consecutive code words in a series of code words, an equal number of transitions from low to high and high to low occur on a subset of the M-links.

Abstract translation: 编码器和解码器电路，用于对一系列代码字进行编码和解码一系列数据字。 数据字包括L个符号。 代码字包括M个符号，其中M大于L.一组紧密耦合的M个链路，用于传送一系列码字中的每一个中的相应符号。 选择码字使得在一系列码字中的每两个连续码字之间，在M链路的子集上出现从低到高和高到低的相等数量的转换。

公开(公告)号：WO2009108562A3

公开(公告)日：2009-11-12

申请号：PCT/US2009034486

申请日：2009-02-19

Applicant: RAMBUS INC ,  ABBASFAR ALIAZAM

Inventor： ABBASFAR ALIAZAM

IPC: G06F11/10

CPC classification number: G06F11/08 ,  G06F11/0793 ,  G06F11/1004

Abstract: Embodiments of a circuit are described. In this circuit, an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links in a channel, where a given driver outputs a given symbol in the set of M symbols onto a given link. Moreover, an error-detection circuit, which is coupled to the encoder circuit, generates and stores error-detection information associated with the set of M symbols, where the error- detection information facilitates subsequent probabilistic determination of a type of error during communication of the set of M symbols to another circuit. Additionally, a receiver circuit receives feedback information from the other circuit. This feedback information includes error information about detection of another type of error in the set of M symbols based on characteristics of the code space. Furthermore, control logic performs remedial action based on the feedback information.

Abstract translation: 描述电路的实施例。 在该电路中，编码器电路将一组N个符号编码为代码空间中的给定码字，其中给定码字包括一组M个符号。 M个驱动器耦合到编码器电路并且耦合到信道中的M个链路，其中给定的驱动器将M个符号集合中的给定符号输出到给定的链路上。 此外，耦合到编码器电路的错误检测电路产生并存储与该M个符号组相关联的错误检测信息，其中错误检测信息有助于在通信期间的错误类型的随后概率确定 一组M符号到另一个电路。 此外，接收器电路从另一电路接收反馈信息。 该反馈信息包括关于基于代码空间的特征来检测M个符号集合中的另一种类型的错误的错误信息。 此外，控制逻辑基于反馈信息执行补救动作。

公开(公告)号：WO2009108562A2

公开(公告)日：2009-09-03

申请号：PCT/US2009/034486

申请日：2009-02-19

Applicant: RAMBUS INC. ,  ABBASFAR, Aliazam

Inventor： ABBASFAR, Aliazam

IPC: H03M13/00

CPC classification number: G06F11/08 ,  G06F11/0793 ,  G06F11/1004

Abstract: Embodiments of a circuit are described. In this circuit, an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links in a channel, where a given driver outputs a given symbol in the set of M symbols onto a given link. Moreover, an error-detection circuit, which is coupled to the encoder circuit, generates and stores error-detection information associated with the set of M symbols, where the error- detection information facilitates subsequent probabilistic determination of a type of error during communication of the set of M symbols to another circuit. Additionally, a receiver circuit receives feedback information from the other circuit. This feedback information includes error information about detection of another type of error in the set of M symbols based on characteristics of the code space. Furthermore, control logic performs remedial action based on the feedback information.

Abstract translation: 描述了电路的实施例。 在该电路中，编码器电路将一组N字符编码为代码空间中的给定码字，其中该给定码字包括一组M symbols个符号。 M个驱动器耦合到编码器电路并且耦合到通道中的M个链路，其中给定的驱动器输出该组M中的给定符号， 我>符号到给定的链接。 此外，耦合到编码器电路的错误检测电路产生并存储与该组M个符号相关的错误检测信息，其中错误检测信息有助于后续的概率性确定 在将该组M个符号传送到另一个电路期间的错误类型。 另外，接收器电路从另一个电路接收反馈信息。 该反馈信息包括关于根据代码空间的特征检测该组符号中的另一种类型的错误的错误信息。 此外，控制逻辑基于反馈信息执行补救行动。

公开(公告)号：WO2008147910A1

公开(公告)日：2008-12-04

申请号：PCT/US2008/064574

申请日：2008-05-22

Applicant: RAMBUS INC. ,  ABBASFAR, Aliazam

Inventor： ABBASFAR, Aliazam

IPC: H04L27/26

CPC classification number: H04L27/2614

Abstract: A communication circuit includes an input node to receive two adjacent blocks of data symbols. A modulator, coupled to the input node, encodes these blocks of data symbols using an encoding technique into corresponding encoded data symbols. Moreover, a detector is coupled to the modulator. This detector determines peak values for each of the encoded data symbols. Furthermore, an amplifier is coupled to the detector, and an output node is coupled to the amplifier. This amplifier amplifies a given encoded data symbol in the encoded data symbols using an associated symbol-dependent gain prior to transmitting this encoded data symbol. Note that the associated symbol-dependent gain is based on an peak value associated with the given encoded data symbol.

Abstract translation: 通信电路包括用于接收数据符号的两个相邻块的输入节点。 耦合到输入节点的调制器使用编码技术将这些数据符号块编码成对应的编码数据符号。 此外，检测器耦合到调制器。 该检测器确定每个编码数据符号的峰值。 此外，放大器耦合到检测器，并且输出节点耦合到放大器。 该放大器在发送该编码数据符号之前使用相关联的符号依赖增益放大编码数据符号中的给定编码数据符号。 注意，相关联的符号相关增益基于与给定编码数据符号相关联的峰值。

公开(公告)号：WO2007127861A2

公开(公告)日：2007-11-08

申请号：PCT/US2007/067536

申请日：2007-04-26

Applicant: RAMBUS INC. ,  THE BOARD OF TRUSTEES OF THE UNIVERSITY OF THE LELAND STANFORD JUNIOR UNIVERSITY ,  ABBASFAR, Aliazam ,  AMIRKHANY, Amir ,  SAVOJ, Jafar

Inventor： ABBASFAR, Aliazam ,  AMIRKHANY, Amir ,  SAVOJ, Jafar

IPC: G06F15/00

CPC classification number: G06F17/5036

Abstract: In a method of characterizing a circuit, a test sequence is provided. A response of the circuit to the test sequence is determined. A transfer function that corresponds to the response is determined. The transfer function is decomposed into a plurality of terms. A respective term corresponds to an nth-order term in an expansion of at least 3rd order that corresponds to the transfer function. A characteristic associated with the circuit is simulated using at least one of the terms in the plurality of terms.

Abstract translation: 在表征电路的方法中，提供测试序列。 确定电路对测试序列的响应。 确定与响应对应的传递函数。 传递函数被分解为多个项。 相应的术语对应于对应于传递函数的至少3阶的扩展中的n阶项。 使用多个术语中的至少一个术语来模拟与电路相关联的特性。