公开(公告)号：WO2013085487A1

公开(公告)日：2013-06-13

申请号：PCT/US2011/063328

申请日：2011-12-05

Applicant: INTEL CORPORATION ,  OZTURK, Erdinc ,  GOPAL, Vinodh ,  WOLRICH, Gilbert M. ,  FEGHALI, Wajda K. ,  GUILFORD, James D. ,  KARAKOYUNLU, Deniz ,  DIXON, Martin G. ,  AKDEMIR, Kahraman D.

Inventor： OZTURK, Erdinc ,  GOPAL, Vinodh ,  WOLRICH, Gilbert M. ,  FEGHALI, Wajda K. ,  GUILFORD, James D. ,  KARAKOYUNLU, Deniz ,  DIXON, Martin G. ,  AKDEMIR, Kahraman D.

IPC: H04K1/00

CPC classification number: G06F21/71 ,  G06F7/723 ,  H04L9/3006 ,  H04L2209/12

Abstract: In one embodiment, the present disclosure provides a method that includes segmenting an n-bit exponent e into a first segment e t and a number t of k-bit segments e i in response to a request to determine a modular exponentiation result R, wherein R is a modular exponentiation of a generator base g for the exponent e and a q-bit modulus m, wherein the generator base g equals two and k is based at least in part on a processor configured to determine the result R; iteratively determining a respective intermediate modular exponentiation result for each segment e i , wherein the determining comprises multiplication, exponentiation and a modular reduction of at least one of a multiplication result and an exponentiation result; and generating the modular exponentiation result R = g e mod m based on, at least in part, at least one respective intermediate modular exponentiation result.

Abstract translation: 在一个实施例中，本公开提供了一种方法，其包括响应于确定模幂运算结果R的请求，将n位指数e分割成第一段et和数目t的k比特段ei，其中R是 指数e的发生器基数g和q位模数m的模幂运算，其中发生器基g等于2，k至少部分地基于被配置为确定结果R的处理器; 迭代地确定每个段ei的相应的中间模幂运算结果，其中所述确定包括相乘结果和求幂结果中的至少一个的乘法，乘法和模块化减少; 并且至少部分地基于至少一个相应的中间模幂运算结果来产生模幂运算结果R = ge mod m。

公开(公告)号：WO2012078378A2

公开(公告)日：2012-06-14

申请号：PCT/US2011/062127

申请日：2011-11-23

Applicant: INTEL CORPORATION ,  GUILFORD, James, D. ,  FEGHALI, Wajdi, K. ,  GOPAL, Vinodh ,  WOLRICH, Gilbert, M. ,  OZTURK, Erdinc ,  DIXON, Martin, G. ,  KARAKOYUNLU, Deniz ,  AKDEMIR, Kahraman, D.

Inventor： GUILFORD, James, D. ,  FEGHALI, Wajdi, K. ,  GOPAL, Vinodh ,  WOLRICH, Gilbert, M. ,  OZTURK, Erdinc ,  DIXON, Martin, G. ,  KARAKOYUNLU, Deniz ,  AKDEMIR, Kahraman, D.

IPC: G06F9/44 ,  G06F9/46 ,  G06F9/06

CPC classification number: G06F9/3851 ,  G06F9/30109 ,  G06F9/4843

Abstract: An embodiment may include circuitry to execute, at least in part, a first list of instructions and/or to concurrently process, at least in part, first and second buffers. The execution of the first list of instructions may result, at least in part, from invocation of a first function call. The first list of instructions may include at least one portion of a second list of instructions interleaved, at least in part, with at least one other portion of a third list of instructions. The portions may be concurrently carried out, at least in part, by one or more sets of execution units of the circuitry. The second and third lists of instructions may implement, at least in part, respective algorithms that are amenable to being invoked by separate respective function calls. The concurrent processing may involve, at least in part, complementary algorithms.

Abstract translation: 实施例可以包括至少部分地执行第一指令列表和/或至少部分地执行第一和第二缓冲器的电路。 第一指令列表的执行可以至少部分地由第一函数调用的调用产生。 第一指令列表可以包括至少部分地与第三指令列表的至少一个其他部分交织的第二指令列表的至少一部分。 这些部分可以至少部分地由电路的一个或多个执行单元同时执行。 第二和第三指令列表可以至少部分地实现适合于通过单独的相应功能调用来调用的相应算法。 并行处理可以至少部分地涉及互补算法。

公开(公告)号：WO2013095615A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067092

申请日：2011-12-23

Applicant: INTEL CORPORATION ,  GOPAL, Vinodh ,  GUILFORD, Jim, D. ,  FEGHALI, Wajdi, K. ,  KARAKOYUNLU, Deniz ,  OZTURK, Erdnic ,  DIXON, Martin ,  AKDEMIR, Kahraman, D. ,  WOLRICH, Gilbert, M.

Inventor： GOPAL, Vinodh ,  GUILFORD, Jim, D. ,  FEGHALI, Wajdi, K. ,  KARAKOYUNLU, Deniz ,  OZTURK, Erdnic ,  DIXON, Martin ,  AKDEMIR, Kahraman, D. ,  WOLRICH, Gilbert, M.

IPC: H03M7/30

CPC classification number: H04L65/607 ,  H03M7/30 ,  H03M7/3086 ,  H04L65/608 ,  H04L69/04 ,  H04L69/22 ,  H04W28/06

Abstract: Methods and apparatus for processing bitstreams and byte streams. According to one aspect, bitstream data is compressed using coalesced string match tokens with delayed matching. A matcher is employed to perform search string match operations using a shortened maximum string length search criteria, resulting in generation of a token stream having data and literal data. A distance match operation is performed on sequentially adjacent tokens to determine if they contain the same distance data. If they do, the len values of the tokens are added through use of a coalesce buffer. Upon detection of a distance non-match, a final coalesced length of a matching string is calculated and output along with the prior matching distance as a coalesced token. Also disclosed is a scheme for writing variable-length tokens into a bitstream under which token data is input into a bit accumulator and written to memory (or cache to be subsequently written to memory) as each token is processed in a manner that eliminates branch mispredict operations associated with detecting whether the bit accumulator is full or close to full.

Abstract translation: 用于处理比特流和字节流的方法和装置。 根据一个方面，使用具有延迟匹配的合并字符串匹配令牌来压缩比特流数据。 使用匹配器来执行搜索字符串匹配操作，使用缩短的最大字符串长度搜索条件，导致生成具有数据和文字数据的令牌流。 对顺序相邻的令牌执行距离匹配操作，以确定它们是否包含相同的距离数据。 如果这样做，令牌的len值通过使用合并缓冲区来添加。 在检测到距离不匹配时，计算匹配串的最终合并长度，并将其与先前匹配距离一起作为合并令牌输出。 还公开了一种用于将可变长度令牌写入比特流的方案，在该比特流中，令牌数据被输入到比特累加器中，并且以消除分支错误预测的方式将每个令牌进行处理，并将其写入存储器（或高速缓存以随后写入存储器） 检测位累加器是满或接近满的操作。

公开(公告)号：WO2012078378A3

公开(公告)日：2012-08-16

申请号：PCT/US2011062127

申请日：2011-11-23

Applicant: INTEL CORP ,  GUILFORD JAMES D ,  FEGHALI WAJDI K ,  GOPAL VINODH ,  WOLRICH GILBERT M ,  OZTURK ERDINC ,  DIXON MARTIN G ,  KARAKOYUNLU DENIZ ,  AKDEMIR KAHRAMAN D

Inventor： GUILFORD JAMES D ,  FEGHALI WAJDI K ,  GOPAL VINODH ,  WOLRICH GILBERT M ,  OZTURK ERDINC ,  DIXON MARTIN G ,  KARAKOYUNLU DENIZ ,  AKDEMIR KAHRAMAN D

IPC: G06F9/44 ,  G06F9/06 ,  G06F9/46

CPC classification number: G06F9/3851 ,  G06F9/30109 ,  G06F9/4843

Abstract: An embodiment may include circuitry to execute, at least in part, a first list of instructions and/or to concurrently process, at least in part, first and second buffers. The execution of the first list of instructions may result, at least in part, from invocation of a first function call. The first list of instructions may include at least one portion of a second list of instructions interleaved, at least in part, with at least one other portion of a third list of instructions. The portions may be concurrently carried out, at least in part, by one or more sets of execution units of the circuitry. The second and third lists of instructions may implement, at least in part, respective algorithms that are amenable to being invoked by separate respective function calls. The concurrent processing may involve, at least in part, complementary algorithms.

Abstract translation: 一个实施例可以包括至少部分地执行第一指令列表和/或至少部分地同时处理第一和第二缓冲器的电路。 指令的第一列表的执行可能至少部分地来自调用第一函数调用。 第一指令列表可以包括至少部分与第三指令列表的至少一个其他部分交织的第二指令列表的至少一部分。 这些部分可以至少部分由电路的一个或多个执行单元同时执行。 指令的第二和第三列表可以至少部分地实现可以由单独的相应函数调用调用的相应算法。 并发处理可以至少部分涉及互补算法。

公开(公告)号：WO2014130338A1

公开(公告)日：2014-08-28

申请号：PCT/US2014/016259

申请日：2014-02-13

Applicant: MARVELL WORLD TRADE LTD. ,  AKDEMIR, Kahraman, D. ,  AYTEK, Tolga, Nihat ,  KARAKOYUNLU, Deniz

Inventor： AKDEMIR, Kahraman, D. ,  AYTEK, Tolga, Nihat ,  KARAKOYUNLU, Deniz

IPC: G06F9/445 ,  G06F9/44

CPC classification number: G06F9/4406 ,  G06F8/66 ,  G06F9/4401

Abstract: The present disclosure describes apparatuses and techniques for patching boot code of read-only memory (ROM). In some aspects, execution of boot code from a ROM is initiated to start a boot process of a device. Execution of the boot code from the ROM is then interrupted to enable execution of other boot code, such as corrected boot code or additional boot code, from another memory. Once the other boot code is executed, execution of the boot code from the ROM is resumed to continue booting the computing device. By so doing, the corrected boot code or additional boot code can be executed during the boot process effective to patch the boot code stored in the ROM.

Abstract translation: 本公开描述了用于修补只读存储器（ROM）的引导代码的装置和技术。 在一些方面，启动来自ROM的引导代码的启动以启动设备的引导过程。 然后从ROM中执行引导代码被中断，以允许从另一个存储器执行其他引导代码，例如修正后的引导代码或其他引导代码。 一旦执行了其他引导代码，则恢复从ROM的引导代码的执行以继续引导计算设备。 通过这样做，可以在引导过程期间执行校正的引导代码或附加引导代码，以有效地修补存储在ROM中的引导代码。