公开(公告)号：WO2013095629A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067165

申请日：2011-12-23

Applicant: INTEL CORPORATION ,  WOLRICH, Gilbert M. ,  YAP, Kirk S. ,  GUILFORD, James D. ,  OZTURK, Erdinc ,  GOPAL, Vinodh ,  FEGHALI, Wajdi K. ,  GULLEY, Sean M. ,  DIXON, Martin G.

Inventor： WOLRICH, Gilbert M. ,  YAP, Kirk S. ,  GUILFORD, James D. ,  OZTURK, Erdinc ,  GOPAL, Vinodh ,  FEGHALI, Wajdi K. ,  GULLEY, Sean M. ,  DIXON, Martin G.

IPC: G06F9/30 ,  G06F9/302

CPC classification number: G06F9/3016 ,  G06F7/525 ,  G06F7/57 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3893

Abstract: An apparatus is described that includes a semiconductor chip having an instruction execution pipeline having one or more execution units with respective logic circuitry to: a) execute a first instruction that multiplies a first input operand and a second input operand and presents a lower portion of the result, where, the first and second input operands are respective elements of first and second input vectors; b) execute a second instruction that multiplies a first input operand and a second input operand and presents an upper portion of the result, where, the first and second input operands are respective elements of first and second input vectors; and, c) execute an add instruction where a carry term of the add instruction's adding is recorded in a mask register.

Abstract translation: 描述了一种装置，其包括具有指令执行流水线的半导体芯片，该指令执行流水线具有一个或多个具有相应逻辑电路的执行单元，以便：a）执行将第一输入操作数与第二输入操作数相乘并且呈现下一部分的第一指令 其中，第一和第二输入操作数是第一和第二输入向量的相应元素; b）执行第二指令，其将第一输入操作数和第二输入操作数相乘并呈现结果的上部，其中第一和第二输入操作数是第一和第二输入向量的相应元素; 以及c）执行加法指令，其中加法指令的相加的进位项被记录在掩码寄存器中。

公开(公告)号：WO2011084214A2

公开(公告)日：2011-07-14

申请号：PCT/US2010054754

申请日：2010-10-29

Applicant: INTEL CORP ,  GOPAL VINODH ,  GUILFORD JAMES D ,  OZTURK ERDINC ,  FEGHALI WAJDI ,  WOLRICH GILBERT M ,  DIXON MARTIN G

Inventor： GOPAL VINODH ,  GUILFORD JAMES D ,  OZTURK ERDINC ,  FEGHALI WAJDI ,  WOLRICH GILBERT M ,  DIXON MARTIN G

IPC: G06F9/305 ,  G06F13/14 ,  G06F13/16

CPC classification number: G06F9/30145 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3893

Abstract: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

Abstract translation: 用于执行换档和异或运算的方法和装置。 在一个实施例中，一种装置包括执行第一指令的执行资源。 响应于第一指令，所述执行资源对至少一个值执行移位和异或。

公开(公告)号：WO2013147877A1

公开(公告)日：2013-10-03

申请号：PCT/US2012/031632

申请日：2012-03-30

Applicant: INTEL CORPORATION ,  YAP, Kirk S. ,  WOLRICH, Gilbert M. ,  GUILFORD, James D. ,  GOPAL, Vinodh ,  OZTURK, Erdinc ,  GULLEY, Sean M. ,  FEGHALI, Wajdi K. ,  DIXON, Martin G.

Inventor： YAP, Kirk S. ,  WOLRICH, Gilbert M. ,  GUILFORD, James D. ,  GOPAL, Vinodh ,  OZTURK, Erdinc ,  GULLEY, Sean M. ,  FEGHALI, Wajdi K. ,  DIXON, Martin G.

IPC: H04L9/28

CPC classification number: G06F9/3016 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30058 ,  G06F9/30098 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/384 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F15/8007 ,  G06F21/602 ,  G06F2212/452 ,  G06F2212/68 ,  H04L9/0643 ,  H04L9/3239 ,  H04L2209/125

Abstract: A processor includes an instruction decoder to receive a first instruction to process a secure hash algorithm 2 (SHA-2) hash algorithm, the first instruction having a first operand associated with a first storage location to store a SHA-2 state and a second operand associated with a second storage location to store a plurality of messages and round constants. The processor further includes an execution unit coupled to the instruction decoder to perform one or more iterations of the SHA-2 hash algorithm on the SHA-2 state specified by the first operand and the plurality of messages and round constants specified by the second operand, in response to the first instruction.

Abstract translation: 处理器包括指令解码器，用于接收处理安全散列算法2（SHA-2）散列算法的第一指令，所述第一指令具有与第一存储位置相关联的第一操作数，以存储SHA-2状态和第二操作数 与第二存储位置相关联以存储多个消息和回合常数。 处理器还包括执行单元，其耦合到指令解码器，以在由第一操作数和由第二操作数指定的多个消息和循环常数指定的SHA-2状态上执行SHA-2散列算法的一个或多个迭代， 响应第一条指令。

公开(公告)号：WO2013095576A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067036

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  GOPAL, Vinodh ,  GUILFORD, James D. ,  WOLRICH, Gilbert M. ,  OZTURK, Erdinc ,  FEGHALI, Wajdi K. ,  YAP, Kirk S. ,  GULLEY, Sean M. ,  DIXON, Martin G. ,  CHAPPELL, Robert S.

Inventor： GOPAL, Vinodh ,  GUILFORD, James D. ,  WOLRICH, Gilbert M. ,  OZTURK, Erdinc ,  FEGHALI, Wajdi K. ,  YAP, Kirk S. ,  GULLEY, Sean M. ,  DIXON, Martin G. ,  CHAPPELL, Robert S.

IPC: G06F9/30 ,  G06F9/305

CPC classification number: G06F9/30043 ,  G06F9/30018 ,  G06F9/34

Abstract: An apparatus and method are described for processing bit streams using bit-oriented instructions. For example, a method according to one embodiment includes the operations of: executing an instruction to get bits for an operation, the instruction identifying a start bit address and a number of bits to be retrieved; retrieving the bits identified by the start bit address and number of bits from a bit-oriented register or cache; and performing a sequence of specified bit operations on the retrieved bits to generate results.

Abstract translation: 描述了一种用于使用面向位的指令来处理比特流的装置和方法。 例如，根据一个实施例的方法包括以下操作：执行用于获得用于操作的比特的指令，所述指令标识起始比特地址和要检索的比特数; 从面向比特的寄存器或高速缓存中检索由起始位地址和位数标识的位; 并对所检索的位执行指定位操作的序列以产生结果。

公开(公告)号：WO2013095504A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066814

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  GOPAL, Vinodh ,  WOLRICH, Gilbert M. ,  YAP, Kirk S. ,  GUILFORD, James D. ,  OZTURK, Erdinc ,  GULLEY, Sean M. ,  FEGHALI, Wajdi K. ,  DIXON, Martin G.

Inventor： GOPAL, Vinodh ,  WOLRICH, Gilbert M. ,  YAP, Kirk S. ,  GUILFORD, James D. ,  OZTURK, Erdinc ,  GULLEY, Sean M. ,  FEGHALI, Wajdi K. ,  DIXON, Martin G.

IPC: G06F9/30 ,  G06F9/305

CPC classification number: H04L9/0631 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30036 ,  H04L9/0643

Abstract: A method is described. The method includes iteratively performing for each position in a result matrix stored in a third register, multiplying a value at a matrix position stored in a first register with a value at a matrix position stored in a second register to obtain a first multiplicative value, where the positions in the first register and the second register are determined by the position in the result matrix and performing an exclusive or (XOR) operation with the first multiplicative value and a value stored at a result matrix position stored in the third register to obtain a result value.

Abstract translation: 描述了一种方法。 该方法包括对存储在第三寄存器中的结果矩阵中的每个位置迭代执行，将存储在第一寄存器中的矩阵位置处的值乘以存储在第二寄存器中的矩阵位置处的值，以获得第一乘法值，其中 第一寄存器和第二寄存器中的位置由结果矩阵中的位置确定，并且执行具有第一乘法值的异或（XOR）操作和存储在存储在第三寄存器中的结果矩阵位置处的值以获得 结果值。

公开(公告)号：WO2013095484A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066733

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  YAP, Kirk S. ,  WOLRICH, Gilbert M. ,  GOPAL, Vinodh ,  GUILFORD, James D. ,  OZTURK, Erdinc ,  GULLEY, Sean M. ,  FEGHALI, Wajdi K. ,  DIXON, Martin G.

Inventor： YAP, Kirk S. ,  WOLRICH, Gilbert M. ,  GOPAL, Vinodh ,  GUILFORD, James D. ,  OZTURK, Erdinc ,  GULLEY, Sean M. ,  FEGHALI, Wajdi K. ,  DIXON, Martin G.

IPC: H04L9/28 ,  H04L9/12

CPC classification number: G06F21/64 ,  H04L9/0643 ,  H04L2209/12

Abstract: A method is described. The method includes executing one or more JH_SBOX_L instruction to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_Permute instruction to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed

Abstract translation: 描述了一种方法。 该方法包括在JH状态下执行一个或多个JH_SBOX_L指令来执行S-Box映射和线性（L）变换，并且一旦S-Box映射和 L变换

公开(公告)号：WO2013066320A1

公开(公告)日：2013-05-10

申请号：PCT/US2011/058802

申请日：2011-11-01

Applicant: INTEL CORPORATION ,  GOPAL, Vinodh ,  GUILFORD, James D. ,  ELDRIDGE, Schuyler ,  WOLRICH, Gilbert M. ,  OZTURK, Erdinc ,  FEGHALI, Wajdi

Inventor： GOPAL, Vinodh ,  GUILFORD, James D. ,  ELDRIDGE, Schuyler ,  WOLRICH, Gilbert M. ,  OZTURK, Erdinc ,  FEGHALI, Wajdi

IPC: G06F17/30 ,  G06F11/10

CPC classification number: G06F17/30303 ,  G06F17/30306 ,  G06F17/3033

Abstract: In one embodiment, circuitry may generate digests to be combined to produce a hash value. The digests may include at least one digest and at least one other digest generated based at least in part upon at least one CRC value and at least one other CRC value. The circuitry may include cyclical redundancy check (CRC) generator circuitry to generate the at least one CRC value based at least in part upon at least one input string. The CRC generator circuitry also may generate the at least one other CRC value based least in part upon at least one other input string. The at least one other input string resulting at least in part from at least one pseudorandom operation involving, at least in part, the at least one input string. Many modifications, variations, and alternatives are possible without departing from this embodiment.

Abstract translation: 在一个实施例中，电路可以生成待组合的摘要以产生散列值。 摘要可以至少部分地基于至少一个CRC值和至少一个其它CRC值来生成至少一个摘要和至少一个其他摘要。 电路可以包括循环冗余校验（CRC）发生器电路，以至少部分地基于至少一个输入串来生成至少一个CRC值。 CRC发生器电路还可以至少部分地基于至少一个其他输入串来生成至少一个其它CRC值。 所述至少一个其他输入字符串至少部分地由至少一个涉及至少一个输入字符串的伪随机操作产生。 在不脱离本实施例的情况下，可以进行许多修改，变型和替换。

公开(公告)号：WO2014105135A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/046410

申请日：2013-06-18

Applicant: INTEL CORPORATION ,  WOLRICH, Gilbert M. ,  YAP, Kirk S. ,  GOPAL, Vinodh ,  GUILFORD, James D.

Inventor： WOLRICH, Gilbert M. ,  YAP, Kirk S. ,  GOPAL, Vinodh ,  GUILFORD, James D.

IPC: G06F21/00

CPC classification number: H04L9/0643 ,  G06F9/30007 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3016 ,  G06F21/602 ,  G06F21/64 ,  G06F21/72

Abstract: A method of an aspect includes receiving an instruction. The instruction indicates a first source of a first packed data including state data elements a i , b i , e i , and f i for a current round (i) of a secure hash algorithm 2 (SHA2) hash algorithm. The instruction indicates a second source of a second packed data. The first packed data has a width in bits that is less than a combined width in bits of eight state data elements a i , b i , c i , d i , e i , f i , g i , h i of the SHA2 hash algorithm. The method also includes storing a result in a destination indicated by the instruction in response to the instruction. The result includes updated state data elements a i+ , b i+ , e i+ , and f i+ that have been updated from the corresponding state data elements a i , b i , e i , and f i by at least one round of the SHA2 hash algorithm.

Abstract translation: 方面的方法包括接收指令。 该指令指示包括安全散列算法2（SHA2）散列算法的当前轮（i）的状态数据元素ai，bi，ei和fi的第一打包数据的第一来源。 该指令指示第二打包数据的第二来源。 第一打包数据具有小于SHA2散列算法的八个状态数据元素ai，bi，ci，di，ei，fi，gi，hi的组合宽度的比特宽度。 该方法还包括响应于指令将结果存储在由指令指示的目的地中。 结果包括已经通过至少一轮的SHA2散列算法从相应的状态数据元素ai，bi，ei和fi更新的更新的状态数据元素ai +，bi +，ei +和fi +。

公开(公告)号：WO2013112118A3

公开(公告)日：2013-10-24

申请号：PCT/US2011066719

申请日：2011-12-22

Applicant: INTEL CORP ,  WOLRICH GILBERT M ,  YAP KIRK S ,  GOPAL VINODH ,  GUILFORD JAMES D ,  OZTURK ERDINC ,  GULLEY SEAN M ,  FEGHALI WAJDI K ,  DIXON MARTIN G

Inventor： WOLRICH GILBERT M ,  YAP KIRK S ,  GOPAL VINODH ,  GUILFORD JAMES D ,  OZTURK ERDINC ,  GULLEY SEAN M ,  FEGHALI WAJDI K ,  DIXON MARTIN G

IPC: G06F17/10 ,  G06F9/06 ,  G06F13/14

CPC classification number: H04L9/14 ,  G06F9/30007 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3893 ,  G06F9/3895 ,  G06F21/602 ,  H04L9/3239

Abstract: A method is described. The method includes executing one or more JH_SBOX_L instructions to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_P instructions to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.

Abstract translation: 描述了一种方法。 该方法包括执行一个或多个JH_SBOX_L指令以执行S-Box映射和在JH状态上的线性（L）变换，并且一旦S-Box映射和所述J-POS映射以及执行一个或多个JH_P指令来执行JH状态的置换功能 L变换。

公开(公告)号：WO2013112118A2

公开(公告)日：2013-08-01

申请号：PCT/US2011/066719

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  WOLRICH, Gilbert, M. ,  YAP, Kirk, S. ,  GOPAL, Vinodh ,  GUILFORD, James, D. ,  OZTURK, Erdinc ,  GULLEY, Sean, M. ,  FEGHALI, Wajdi, K. ,  DIXON, Martin, G.

Inventor： WOLRICH, Gilbert, M. ,  YAP, Kirk, S. ,  GOPAL, Vinodh ,  GUILFORD, James, D. ,  OZTURK, Erdinc ,  GULLEY, Sean, M. ,  FEGHALI, Wajdi, K. ,  DIXON, Martin, G.

IPC: G06F17/10 ,  G06F9/06 ,  G06F13/14

CPC classification number: H04L9/14 ,  G06F9/30007 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3893 ,  G06F21/602 ,  H04L9/3239

Abstract: A method is described. The method includes executing one or more JH_SBOX_L instructions to perform S-Box mappings and a linear (L) transformation on a JH state and executing one or more JH_P instructions to perform a permutation function on the JH state once the S-Box mappings and the L transformation have been performed.

Abstract translation: 描述了一种方法。 该方法包括执行一个或多个JH_SBOX_L指令以对JH状态执行S-Box映射和线性（L）变换，并且一旦执行了一个或多个JH_P指令就对JH状态执行置换功能，一旦S盒映射和 L转换已经完成。