公开(公告)号：WO2017030600A1

公开(公告)日：2017-02-23

申请号：PCT/US2015/065134

申请日：2015-12-10

Applicant: INTEL CORPORATION ,  WOLRICH, Gilbert M. ,  GOPAL, Vinodh ,  GULLEY, Sean M. ,  YAP, Kirk S. ,  FEGHALI, Wajdi K.

Inventor： WOLRICH, Gilbert M. ,  GOPAL, Vinodh ,  GULLEY, Sean M. ,  YAP, Kirk S. ,  FEGHALI, Wajdi K.

IPC: H04L9/06 ,  H04L9/32 ,  G06F9/38 ,  G06F15/80

CPC classification number: G06F9/30145 ,  G06F9/30007 ,  G06F9/30036 ,  G06F21/72

Abstract: Instructions and logic provide SIMD SM3 cryptographic hashing functionality. Some embodiments include a processor comprising: a decoder to decode instructions for a SIMD SM3 message expansion, specifying first and second source data operand sets, and an expansion extent. Processor execution units, responsive to the instruction, perform a number of SM3 message expansions, from the first and second source data operand sets, determined by the specified expansion extent and store the result into a SIMD destination register. Some embodiments also execute instructions for a SIMD SM3 hash round-slice portion of the hashing algorithm, from an intermediate hash value input, a source data set, and a round constant set. Processor execution units perform a set of SM3 hashing round iterations upon the source data set, applying the intermediate hash value input and the round constant set, and store a new hash value result in a SIMD destination register.

Abstract translation: 说明和逻辑提供SIMD SM3加密散列功能。 一些实施例包括处理器，包括：解码器，用于解码SIMD SM3消息扩展的指令，指定第一和第二源数据操作数集合以及扩展范围。 响应于指令的处理器执行单元从由指定扩展范围确定的第一和第二源数据操作数集执行多个SM3消息扩展，并将结果存储到SIMD目的地寄存器中。 一些实施例还从中间散列值输入，源数据集和圆常数集合执行散列算法的SIMD SM3散列圆切片部分的指令。 处理器执行单元在源数据集上执行一组SM3散列循环迭代，应用中间散列值输入和循环常数集合，并将新的散列值结果存储在SIMD目的寄存器中。

公开(公告)号：WO2013095547A9

公开(公告)日：2013-09-06

申请号：PCT/US2011066988

申请日：2011-12-22

Applicant: INTEL CORP ,  WOLRICH GILBERT M ,  YAP KIRK S ,  GUILFORD JAMES D ,  OZTURK ERDINC ,  GOPAL VINODH ,  FEGHALI WAJDI K ,  GULLEY SEAN M ,  DIXON MARTIN G

Inventor： WOLRICH GILBERT M ,  YAP KIRK S ,  GUILFORD JAMES D ,  OZTURK ERDINC ,  GOPAL VINODH ,  FEGHALI WAJDI K ,  GULLEY SEAN M ,  DIXON MARTIN G

IPC: G06F1/00 ,  G06F9/305 ,  G06F9/44

CPC classification number: G06F9/30029 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3895 ,  H04L9/0643

Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows. a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.

Abstract translation: 描述了包括指令流水线内的执行单元的装置。 执行单元具有包括a）和b）的电路的多个级，如下所述。 a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）用于接收第一四进制字的第一输入和用于接收第二四字的第二输入; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）具有耦合到第二输入的相应输入的旋转器; iv）具有耦合到加法器的输出的第一输入和耦合到转子的输出的第二输入的异或门。 b）具有耦合到多个混合逻辑部分的相应加法器和异或门输出的输入的置换逻辑电路。

公开(公告)号：WO2013095648A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067230

申请日：2011-12-23

Applicant: INTEL CORPORATION ,  FEGHALI, Wajdi K. ,  GOPAL, Vinodh ,  GUILFORD, James D. ,  OZTURK, Erdinc ,  WOLRICH, Gilbert M. ,  YAP, Kirk S. ,  GULLEY, Sean M. ,  DIXON, Martin G.

Inventor： FEGHALI, Wajdi K. ,  GOPAL, Vinodh ,  GUILFORD, James D. ,  OZTURK, Erdinc ,  WOLRICH, Gilbert M. ,  YAP, Kirk S. ,  GULLEY, Sean M. ,  DIXON, Martin G.

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/38

CPC classification number: G06F21/602 ,  G06F9/30007 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30094 ,  G06F9/30181

Abstract: A method is described that includes performing the following within an instruction execution pipeline implemented on a semiconductor chip: summing three input vector operands through execution of a single instruction; and, not raising any arithmetic flags even though a result of the summing creates more bits than circuitry designed to transport the summation is able to transport.

Abstract translation: 描述了一种方法，其包括在半导体芯片上实现的指令执行流水线内执行以下操作：通过执行单个指令对三个输入向量操作数相加; 并且，即使求和的结果产生比设计用于传送求和的电路更多的位能够传输，也不会提高任何算术标记。

公开(公告)号：WO2013095615A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/067092

申请日：2011-12-23

Applicant: INTEL CORPORATION ,  GOPAL, Vinodh ,  GUILFORD, Jim, D. ,  FEGHALI, Wajdi, K. ,  KARAKOYUNLU, Deniz ,  OZTURK, Erdnic ,  DIXON, Martin ,  AKDEMIR, Kahraman, D. ,  WOLRICH, Gilbert, M.

Inventor： GOPAL, Vinodh ,  GUILFORD, Jim, D. ,  FEGHALI, Wajdi, K. ,  KARAKOYUNLU, Deniz ,  OZTURK, Erdnic ,  DIXON, Martin ,  AKDEMIR, Kahraman, D. ,  WOLRICH, Gilbert, M.

IPC: H03M7/30

CPC classification number: H04L65/607 ,  H03M7/30 ,  H03M7/3086 ,  H04L65/608 ,  H04L69/04 ,  H04L69/22 ,  H04W28/06

Abstract: Methods and apparatus for processing bitstreams and byte streams. According to one aspect, bitstream data is compressed using coalesced string match tokens with delayed matching. A matcher is employed to perform search string match operations using a shortened maximum string length search criteria, resulting in generation of a token stream having data and literal data. A distance match operation is performed on sequentially adjacent tokens to determine if they contain the same distance data. If they do, the len values of the tokens are added through use of a coalesce buffer. Upon detection of a distance non-match, a final coalesced length of a matching string is calculated and output along with the prior matching distance as a coalesced token. Also disclosed is a scheme for writing variable-length tokens into a bitstream under which token data is input into a bit accumulator and written to memory (or cache to be subsequently written to memory) as each token is processed in a manner that eliminates branch mispredict operations associated with detecting whether the bit accumulator is full or close to full.

Abstract translation: 用于处理比特流和字节流的方法和装置。 根据一个方面，使用具有延迟匹配的合并字符串匹配令牌来压缩比特流数据。 使用匹配器来执行搜索字符串匹配操作，使用缩短的最大字符串长度搜索条件，导致生成具有数据和文字数据的令牌流。 对顺序相邻的令牌执行距离匹配操作，以确定它们是否包含相同的距离数据。 如果这样做，令牌的len值通过使用合并缓冲区来添加。 在检测到距离不匹配时，计算匹配串的最终合并长度，并将其与先前匹配距离一起作为合并令牌输出。 还公开了一种用于将可变长度令牌写入比特流的方案，在该比特流中，令牌数据被输入到比特累加器中，并且以消除分支错误预测的方式将每个令牌进行处理，并将其写入存储器（或高速缓存以随后写入存储器） 检测位累加器是满或接近满的操作。

公开(公告)号：WO2011084214A3

公开(公告)日：2011-07-14

申请号：PCT/US2010/054754

申请日：2010-10-29

Applicant: INTEL CORPORATION ,  GOPAL, Vinodh ,  GUILFORD, James D. ,  OZTURK, Erdinc ,  FEGHALI, Wajdi ,  WOLRICH, Gilbert M. ,  DIXON, Martin G.

Inventor： GOPAL, Vinodh ,  GUILFORD, James D. ,  OZTURK, Erdinc ,  FEGHALI, Wajdi ,  WOLRICH, Gilbert M. ,  DIXON, Martin G.

IPC: G06F9/305 ,  G06F13/14 ,  G06F13/16

Abstract: Method and apparatus for performing a shift and XOR operation. In one embodiment, an apparatus includes execution resources to execute a first instruction. In response to the first instruction, said execution resources perform a shift and XOR on at least one value.

公开(公告)号：WO2007078939A2

公开(公告)日：2007-07-12

申请号：PCT/US2006/048417

申请日：2006-12-18

Applicant: INTEL CORPORATION ,  FEGHALI, Wajdi, K. ,  HASENPLAUGH, William, C. ,  WOLRICH, Gilbert, M. ,  CUTTER, Daniel, F. ,  GOPAL, Vinodh ,  GAUBATZ, Gunnar

Inventor： FEGHALI, Wajdi, K. ,  HASENPLAUGH, William, C. ,  WOLRICH, Gilbert, M. ,  CUTTER, Daniel, F. ,  GOPAL, Vinodh ,  GAUBATZ, Gunnar

IPC: G06F7/525

CPC classification number: G06F7/5275

Abstract: In general, in one aspect, the disclosure describes a multiplier that includes a set of multiple multipliers configured in parallel where the set of multiple multipliers have access to a first operand and a second operand to multiply, the first operand having multiple segments and the second operand having multiple segments. The multiplier also includes logic to repeatedly supply a single segment of the second operand to each multiplier of the set of multiple multipliers and to supply multiple respective segments of the first operand to the respective ones of the set of multiple multipliers until each segment of the second operand has been supplied with each segment of the first operand. The logic shifts the output of different ones of the set of multiple multipliers based, at least in part, on the position of the respective segments within the first operand. The multiplier also includes an accumulator coupled to the logic.

Abstract translation: 一般来说，在一个方面，本发明描述了一种乘法器，其包括并行配置的一组多个乘法器，其中多个乘法器的集合具有对第一操作数的访问和第二操作数的乘法，第一操作数具有多个段，第二操作数具有多个段 具有多个段的操作数。 所述乘法器还包括逻辑以将所述第二操作数的单个段重复地提供给所述多个乘法器集合的每个乘法器，并且将所述第一操作数的多个相应段提供给所述多个乘法器组中的各个乘法器，直到所述第二 操作数已被提供给第一个操作数的每个段。 该逻辑至少部分地基于第一操作数内的相应段的位置来移动多个乘法器组中不同的乘法器的输出。 乘法器还包括耦合到逻辑的累加器。

公开(公告)号：WO2013095529A9

公开(公告)日：2013-10-17

申请号：PCT/US2011066941

申请日：2011-12-22

Applicant: INTEL CORP ,  GOPAL VINODH ,  GUILFORD JAMES D ,  WOLRICH GILBERT M ,  FEGHALI WAJDI K ,  OZTURK ERDINC ,  DIXON MARTIN G ,  MIRKES SEAN P ,  MERTEN MATTHEW C ,  LI TONG ,  TOLL BRET L

Inventor： GOPAL VINODH ,  GUILFORD JAMES D ,  WOLRICH GILBERT M ,  FEGHALI WAJDI K ,  OZTURK ERDINC ,  DIXON MARTIN G ,  MIRKES SEAN P ,  MERTEN MATTHEW C ,  LI TONG ,  TOLL BRET L

IPC: G06F9/30 ,  G06F9/305 ,  G06F13/14

CPC classification number: G06F9/3001 ,  G06F9/30094 ,  G06F9/3838

Abstract: A number of addition instructions are provided that have no data dependency between each other. A first addition instruction stores its carry output in a first flag of a flags register without modifying a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register without modifying the first flag in the flags register.

Abstract translation: 提供了彼此之间没有数据依赖性的多个附加指令。 第一加法指令将其进位输出存储在标志寄存器的第一标志中，而不修改标志寄存器中的第二标志。 第二加法指令将其进位输出存储在标志寄存器的第二标志中，而不修改标志寄存器中的第一个标志。

公开(公告)号：WO2013095547A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066988

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  WOLRICH, Gilbert M. ,  YAP, Kirk S. ,  GUILFORD, James D. ,  OZTURK, Erdinc ,  GOPAL, Vinodh ,  FEGHALI, Wajdi K. ,  GULLEY, Sean M. ,  DIXON, Martin G.

Inventor： WOLRICH, Gilbert M. ,  YAP, Kirk S. ,  GUILFORD, James D. ,  OZTURK, Erdinc ,  GOPAL, Vinodh ,  FEGHALI, Wajdi K. ,  GULLEY, Sean M. ,  DIXON, Martin G.

IPC: G06F1/00 ,  G06F9/305 ,  G06F9/44

CPC classification number: G06F9/30029 ,  G06F9/30007 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/3885 ,  G06F9/3895 ,  H04L9/0643

Abstract: An apparatus is described that includes an execution unit within an instruction pipeline. The execution unit has multiple stages of a circuit that includes a) and b) as follows. a) a first logic circuitry section having multiple mix logic sections each having: i) a first input to receive a first quad word and a second input to receive a second quad word; ii) an adder having a pair of inputs that are respectively coupled to the first and second inputs; iii) a rotator having a respective input coupled to the second input; iv) an XOR gate having a first input coupled to an output of the adder and a second input coupled to an output of the rotator. b) permute logic circuitry having inputs coupled to the respective adder and XOR gate outputs of the multiple mix logic sections.

Abstract translation: 描述了一种包括指令流水线内的执行单元的装置。 执行单元具有多级电路，其包括a）和b）如下。 a）具有多个混合逻辑部分的第一逻辑电路部分，每个混合逻辑部分具有：i）接收第一四进制字的第一输入和接收第二四进制字的第二输入; ii）具有分别耦合到第一和第二输入的一对输入的加法器; iii）旋转器，具有耦合到第二输入的相应输入; iv）XOR门，具有耦合到加法器的输出的第一输入和耦合到旋转器的输出的第二输入。 b）置换逻辑电路，其具有耦合到相应加法器的输入和多个混合逻辑部分的异或门输出。

公开(公告)号：WO2013095521A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066898

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  WOLRICH, Gilbert, M. ,  YAP, Kirk, S. ,  GUILFORD, James, D. ,  GOPAL, Vinodh ,  OZTURK, Erdinc ,  GULLEY, Sean, M. ,  FEGHALI, Wajdi, K. ,  DIXON, Martin, G.

Inventor： WOLRICH, Gilbert, M. ,  YAP, Kirk, S. ,  GUILFORD, James, D. ,  GOPAL, Vinodh ,  OZTURK, Erdinc ,  GULLEY, Sean, M. ,  FEGHALI, Wajdi, K. ,  DIXON, Martin, G.

IPC: H04L9/28 ,  H04L9/12

CPC classification number: H04L9/28 ,  G06F9/30007 ,  G06F9/30036 ,  G06F21/72 ,  H04L9/0643 ,  H04L2209/122

Abstract: A method of an aspect includes receiving an instruction indicating a first source having at least one set of four state matrix data elements, which represent a complete set of four inputs to a G function of a cryptographic hashing algorithm. The algorithm uses a sixteen data element state matrix, and alternates between updating data elements in columns and diagonals. The instruction also indicates a second source having data elements that represent message and constant data. In response to the instruction, a result is stored in a destination indicated by the instruction. The result includes updated state matrix data elements including at least one set of four updated state matrix data elements. Each of the four updated state matrix data elements represents a corresponding one of the four state matrix data elements of the first source, which has been updated by the G function.

Abstract translation: 一种方面的方法包括：接收指示具有至少一组四个状态矩阵数据元素的第一源的指令，其表示对密码散列算法的G函数的四个输入的完整集合。 该算法使用十六个数据元素状态矩阵，并在列和对角线之间更新数据元素。 该指令还指示具有表示消息和常数数据的数据元素的第二源。 响应该指令，结果存储在指令指示的目的地中。 结果包括更新的状态矩阵数据元素，包括至少一组四个更新的状态矩阵数据元素。 四个更新的状态矩阵数据元素中的每一个表示已由G功能更新的第一源的四个状态矩阵数据元素中的相应一个。

公开(公告)号：WO2013089682A1

公开(公告)日：2013-06-20

申请号：PCT/US2011/064640

申请日：2011-12-13

Applicant: INTEL CORPORATION ,  YAP, Kirk S. ,  WOLRICH, Gilbert M. ,  GUILFORD, James D. ,  GOPAL, Vinodh ,  OZTURK, Erdinc ,  GULLEY, Sean M. ,  FEGHALI, Wajdi K. ,  DIXON, Martin G.

Inventor： YAP, Kirk S. ,  WOLRICH, Gilbert M. ,  GUILFORD, James D. ,  GOPAL, Vinodh ,  OZTURK, Erdinc ,  GULLEY, Sean M. ,  FEGHALI, Wajdi K. ,  DIXON, Martin G.

IPC: G06F9/30 ,  G06F9/305 ,  G06F21/22 ,  H04L9/28

CPC classification number: G06F9/30145 ,  H04L9/0643 ,  H04L2209/122

Abstract: A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner.

Abstract translation: 处理器包括多个寄存器，指令解码器，用于接收处理表示KECCAK散列算法的KECCAK状态的数据的KECCAK状态立方体的指令，以将KECCAK状态立方体分割成多个子单元，并存储子单元 分别在多个寄存器中，以及执行单元，其耦合到指令解码器，以向量方式分别存储在多个寄存器中的多个子数据块上执行KECCAK散列算法。