公开(公告)号：WO2019005157A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040496

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  WIEGAND, Christopher J. ,  RAHMAN, Tofizur ,  OUELLETTE, Daniel G. ,  SMITH, Angeline K. ,  BROCKMAN, Justin S. ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOCZY, Mark L. ,  DOYLE, Brian S. ,  GOLONZKA, Oleg ,  ALZATE VINASCO, Juan G.

Inventor： WIEGAND, Christopher J. ,  RAHMAN, Tofizur ,  OUELLETTE, Daniel G. ,  SMITH, Angeline K. ,  BROCKMAN, Justin S. ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOCZY, Mark L. ,  DOYLE, Brian S. ,  GOLONZKA, Oleg ,  ALZATE VINASCO, Juan G.

IPC: H01L43/10 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: A memory device includes a bottom electrode disposed above a substrate, a fixed magnet disposed above the bottom electrode, a tunnel barrier including a magnesium oxide disposed on the fixed magnet, a free magnet on the tunnel barrier, a cap oxide layer disposed on the free magnet, a follower magnet disposed on the oxide layer and a metallic cap disposed on the follower magnet. The metallic cap includes a metal such as Hf, W and Ta and further includes a trace amounts of an inert gas. One or more conductive nano-channels extend from the metallic cap through the free magnet and into the oxide layer, where each of the one or more conductive nano-channels include the material of the metallic cap. The memory device further includes an etch stop layer disposed on the metallic cap and a top electrode disposed on the etch stop layer.

公开(公告)号：WO2019125497A1

公开(公告)日：2019-06-27

申请号：PCT/US2017/068359

申请日：2017-12-22

Applicant: INTEL CORPORATION ,  LAJOIE, Travis ,  GHANI, Tahir ,  KAVALIEROS, Jack T. ,  OGADHOH, Shem O. ,  WANG, Yih ,  SELL, Bernhard ,  GARDINER, Allen ,  LIN, Blake ,  ALZATE VINASCO, Juan G. ,  WANG, Pei-Hua ,  KU, Chieh-Jen ,  SHARMA, Abhishek A.

Inventor： LAJOIE, Travis ,  GHANI, Tahir ,  KAVALIEROS, Jack T. ,  OGADHOH, Shem O. ,  WANG, Yih ,  SELL, Bernhard ,  GARDINER, Allen ,  LIN, Blake ,  ALZATE VINASCO, Juan G. ,  WANG, Pei-Hua ,  KU, Chieh-Jen ,  SHARMA, Abhishek A.

IPC: H01L21/768

Abstract: Embodiments herein describe techniques for a semiconductor device having an interconnect structure above a substrate. The interconnect structure may include an inter-level dielectric (ILD) layer and a separation layer above the ILD layer. A first conductor and a second conductor may be within the ILD layer. The first conductor may have a first physical configuration, and the second conductor may have a second physical configuration different from the first physical configuration. Other embodiments may be described and/or claimed.

公开(公告)号：WO2019182589A1

公开(公告)日：2019-09-26

申请号：PCT/US2018/023632

申请日：2018-03-21

Applicant: INTEL CORPORATION ,  RAHMAN, Tofizur ,  WIEGAND, Christopher J. ,  BROCKMAN, Christopher ,  OUELLETTE, Daniel G. ,  ALZATE VINASCO, Juan G. ,  SMITH, Angeline K. ,  GOLONZKA, Oleg

Inventor： RAHMAN, Tofizur ,  WIEGAND, Christopher J. ,  BROCKMAN, Christopher ,  OUELLETTE, Daniel G. ,  ALZATE VINASCO, Juan G. ,  SMITH, Angeline K. ,  GOLONZKA, Oleg

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A memory device comprises a perpendicular magnetic tunnel junction (PMTJ) stack disposed above a substrate. The PMTJ stack has a first free layer magnet, a reference fixed magnet, and a barrier material between the first free layer magnet and the reference fixed magnet. A material stack is on the PMTJ device, where the material stack comprises a first cap material, a second free layer magnet, and a perpendicular magnetic anisotropy (PMA) booster material to increase PMA of the PMTJ stack.

公开(公告)号：WO2019005160A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040500

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  OUELLETTE, Daniel G. ,  WU, Stephen Y. ,  BROCKMAN, Justin S. ,  WIEGAND, Christopher J. ,  GOLONZKA, Oleg ,  RAHMAN, Tofizur ,  SMITH, Angeline K. ,  DOYLE, Brian S. ,  ALZATE VINASCO, Juan G. ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOCZY, Mark L.

Inventor： OUELLETTE, Daniel G. ,  WU, Stephen Y. ,  BROCKMAN, Justin S. ,  WIEGAND, Christopher J. ,  GOLONZKA, Oleg ,  RAHMAN, Tofizur ,  SMITH, Angeline K. ,  DOYLE, Brian S. ,  ALZATE VINASCO, Juan G. ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOCZY, Mark L.

IPC: H01L43/10 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: A memory device includes a bottom electrode comprising a non-stoichiometric tantalum nitride layer. A synthetic antiferromagnetic layer is disposed above the bottom electrode. A fixed magnet is disposed above the synthetic antiferromagnetic layer. A tunnel barrier is disposed above the fixed magnet. A free magnet is above the tunnel barrier and a top electrode is disposed above the free magnet.

公开(公告)号：WO2018125085A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/068904

申请日：2016-12-28

Applicant: INTEL CORPORATION ,  BROCKMAN, Justin ,  WIEGAND, Christopher ,  RAHMAN, MD Tofizur ,  OUELETTE, Daniel ,  SMITH, Angeline ,  ALZATE VINASCO, Juan ,  KUO, Charles ,  DOCZY, Mark ,  OGUZ, Kaan ,  O'BRIEN, Kevin ,  DOYLE, Brian ,  GOLONZKA, Oleg ,  GHANI, Tahir

Inventor： BROCKMAN, Justin ,  WIEGAND, Christopher ,  RAHMAN, MD Tofizur ,  OUELETTE, Daniel ,  SMITH, Angeline ,  ALZATE VINASCO, Juan ,  KUO, Charles ,  DOCZY, Mark ,  OGUZ, Kaan ,  O'BRIEN, Kevin ,  DOYLE, Brian ,  GOLONZKA, Oleg

IPC: H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.