公开(公告)号：WO2013101237A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/068269

申请日：2011-12-31

Applicant: INTEL CORPORATION ,  JHAVERI, Ritesh ,  SELL, Bernhard Ben ,  GHANI, Tahir

Inventor： JHAVERI, Ritesh ,  SELL, Bernhard Ben ,  GHANI, Tahir

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/0638 ,  H01L21/823431 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785

Abstract: A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin. The second hard mask layer is removed, while the hard mask etch stop layer remains to protect the top surface of the fin during subsequent fabrication steps.

Abstract translation: 在高鳍的顶表面上形成硬掩模蚀刻停止件，以保持翅片高度，并且在晶体管制造过程的蚀刻步骤期间保护翅片的顶表面免受损坏。 在一个实施例中，使用双硬掩模系统形成硬掩模蚀刻停止件，其中在衬底的表面上形成硬掩模蚀刻停止层，并且使用第二硬掩模层来用硬掩模 在鳍的顶表面上的蚀刻停止层。 去除第二硬掩模层，同时保留硬掩模蚀刻停止层以在随后的制造步骤期间保护翅片的顶表面。

公开(公告)号：WO2006039641A2

公开(公告)日：2006-04-13

申请号：PCT/US2005035474

申请日：2005-09-29

Applicant: INTEL CORP ,  HOFFMANN THOMAS ,  TYAGI SUNIT ,  CURELLO GIUSEPPE ,  SELL BERNHARD ,  AUTH CHRISTOPHER

Inventor： HOFFMANN THOMAS ,  TYAGI SUNIT ,  CURELLO GIUSEPPE ,  SELL BERNHARD ,  AUTH CHRISTOPHER

IPC: H01L21/336 ,  H01L21/265 ,  H01L29/78

CPC classification number: H01L29/66636 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/41783 ,  H01L29/66492 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method of providing a halo implant region in a substrate of a MOS device having a gate electrode thereon and defining source/drain regions, a MOS device fabricated according to the above method, and a system comprising the MOS device. The method comprises: defining undercut recesses in the substrate at the source/drain regions thereof, the undercut recesses extending beneath the gate electrode; creating a halo implant region beneath the gate electrode between the recesses; and providing raised source/drain structures in the undercut recesses after creating the halo implant region.

Abstract translation: 一种在其上具有栅极并限定源极/漏极区的MOS器件的衬底中提供晕环注入区的方法，根据上述方法制造的MOS器件以及包括该MOS器件的系统。 该方法包括：在衬底的源/漏区处限定底切凹槽，底切凹槽在栅电极下方延伸; 在凹槽之间的栅电极下方形成晕环注入区; 以及在形成光晕注入区之后在底切凹槽中提供凸起的源极/漏极结构。

公开(公告)号：WO2010002718A2

公开(公告)日：2010-01-07

申请号：PCT/US2009048764

申请日：2009-06-26

Applicant: INTEL CORP ,  SELL BERNHARD ,  GOLONZKA OLEG

Inventor： SELL BERNHARD ,  GOLONZKA OLEG

IPC: H01L21/28

CPC classification number: H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IlD disposed on a top surface of a metal gate disposed on the substrate.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括形成包括设置在基板的源极/漏极接触件上的第一接触金属和设置在第一接触金属的顶表面上的第二接触金属的结构，其中第二接触金属设置在设置的IID内 在设置在基板上的金属栅极的顶面上。

公开(公告)号：WO2009017997A1

公开(公告)日：2009-02-05

申请号：PCT/US2008/070604

申请日：2008-07-21

Applicant: INTEL CORPORATION ,  RACHMADY, Willy ,  KEATING, Steven ,  SELL, Bernhard

Inventor： RACHMADY, Willy ,  KEATING, Steven ,  SELL, Bernhard

IPC: H01L21/8238

CPC classification number: H01L21/823807 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A method for forming a semiconductor device having abrupt ultra shallow epi-tip regions comprises forming a gate stack on a crystalline substrate, performing a first ion implantation process to amorphisize a first pair of regions of the substrate disposed adjacent to and on laterally opposite sides of the gate stack, forming a pair of spacers on the substrate disposed on laterally opposite sides of the gate stack, performing a second ion implantation process to amorphisize a second pair of regions of the substrate that are disposed on laterally opposite sides of the gate stack and adjacent to the spacers, applying a selective wet etch chemistry to remove the amorphisized first and second pair of regions and form a pair of cavities on laterally opposite sides of the gate stack, and depositing a silicon alloy in the pair of cavities to form source and drain regions and source and drain epi-tip regions.

Abstract translation: 一种用于形成具有突变的超浅表面尖端区域的半导体器件的方法包括在晶体衬底上形成栅极堆叠，执行第一离子注入工艺以使位于邻近和相对侧两侧的衬底的第一对区域非晶化 所述栅堆叠在所述衬底上形成一对间隔物，所述衬底设置在所述栅堆叠的横向相对侧上，执行第二离子注入工艺以使位于所述栅叠层的横向相对侧上的所述衬底的第二对区域非晶化;以及 邻近所述间隔物，施加选择性湿法蚀刻化学物质以去除所述非晶化的第一和第二对区域并在所述栅极堆叠的横向相对侧上形成一对空腔，以及在所述一对空腔中沉积硅合金以形成源和 漏极区域和源极和漏极表面尖端区域。

公开(公告)号：WO2006074438A1

公开(公告)日：2006-07-13

申请号：PCT/US2006/000686

申请日：2006-01-05

Applicant: INTEL CORPORATION ,  CURELLO, Guiseppe ,  SELL, Bernhard ,  TYAGI, Sunit ,  AUTH, Chris

Inventor： CURELLO, Guiseppe ,  SELL, Bernhard ,  TYAGI, Sunit ,  AUTH, Chris

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7842

Abstract: Embodiments of the invention provide a transistor with stepped source and drain regions. The stepped regions may provide significant strain in a channel region while minimizing current leakage. The stepped regions may be formed by forming two recesses in a substrate to result in a stepped recess, and forming the source/drain regions in the recesses.

Abstract translation: 本发明的实施例提供具有阶梯式源极和漏极区域的晶体管。 台阶区域可以在通道区域中提供显着的应变，同时最小化电流泄漏。 可以通过在基板中形成两个凹槽来形成阶梯状区域，以形成阶梯形凹陷，并且在凹部中形成源极/漏极区域。

公开(公告)号：WO2006039641A3

公开(公告)日：2006-04-13

申请号：PCT/US2005/035474

申请日：2005-09-29

Applicant: INTEL CORPORATION ,  HOFFMANN, Thomas ,  TYAGI, Sunit ,  CURELLO, Giuseppe ,  SELL, Bernhard ,  AUTH, Christopher

Inventor： HOFFMANN, Thomas ,  TYAGI, Sunit ,  CURELLO, Giuseppe ,  SELL, Bernhard ,  AUTH, Christopher

IPC: H01L21/336 ,  H01L29/78 ,  H01L21/265

Abstract: A method of providing a halo implant region in a substrate of a MOS device having a gate electrode thereon and defining source/drain regions, a MOS device fabricated according to the above method, and a system comprising the MOS device. The method comprises: defining undercut recesses in the substrate at the source/drain regions thereof, the undercut recesses extending beneath the gate electrode; creating a halo implant region beneath the gate electrode between the recesses; and providing raised source/drain structures in the undercut recesses after creating the halo implant region.

公开(公告)号：WO2003017342A3

公开(公告)日：2003-02-27

申请号：PCT/DE2002/002651

申请日：2002-07-18

Applicant: INFINEON TECHNOLOGIES AG ,  GOLDBACH, Matthias ,  HECHT, Thomas ,  LÜTZEN, Jörn ,  SELL, Bernhard

Inventor： GOLDBACH, Matthias ,  HECHT, Thomas ,  LÜTZEN, Jörn ,  SELL, Bernhard

IPC: H01L21/027

Abstract: Eine Struktur auf einer Schichtenoberfläche des Halbleiter-Wafers weist zumindest einen für elektromagnetische Strahlung reflektierenden ersten Flächenbereich (8,9) und zumindest einen zweiten, im Wesentlichen nicht reflektierenden Flächenbereich (10,11,12) auf. Auf diese Schichtenoberfläche wird eine lichtdurchläßige Isolationsschicht (13) und eine lichtempfindliche Schicht erzeugt. Die elektromagnetische Strahlung wird mit einem Einfallswinkel θ auf die lichtempfindliche Schicht gerichtet und die Struktur der Schichtenoberfläche mit einem lateralen Ersatz in die lichtempfindliche Schicht abgebildet.

公开(公告)号：WO2002088419A1

公开(公告)日：2002-11-07

申请号：PCT/EP2002/004521

申请日：2002-04-24

Applicant: INFINEON TECHNOLOGIES AG ,  SELL, Bernhard ,  SÄNGER, Annette ,  HECHT, Thomas

Inventor： SELL, Bernhard ,  SÄNGER, Annette ,  HECHT, Thomas

IPC: C23C16/02

CPC classification number: H01L21/28194 ,  C23C16/0272 ,  H01L21/28079 ,  H01L21/28211 ,  H01L21/28518 ,  H01L21/3141 ,  H01L21/31645 ,  H01L21/76802 ,  H01L21/76831 ,  H01L28/60 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

Abstract: Verfahren zum Erzeugen einer metallischen oder metallhaltigen Schicht (5) unter Verwendung eines Präkursors auf einer silizium- oder germaniumhaltigen Schicht insbesondere eines elektronischen Bauelements, bei dem auf die silizium- oder germanium-haltige Schicht (3) vor der Verwendung des Präkursors eine Zwischenschicht (4) aufgebracht wird, die zumindest für die Elemente des Präkursors, die die silizium- oder germaniumhaltige Schicht ätzen würden, eine Diffusionsbarriere bildet und selbst gegenüber dem Praäkursor ätzresistent ist.

Abstract translation: 一种用于生产使用上的硅或含锗层的前体的金属或含金属的层（5），特别是电子部件，方法，其中所述硅或层含锗（3）使用所述前体，中间层之前（4- ）被施加，其形成扩散阻挡至少对于将蚀刻含硅或含锗层的前体的元件和本身是蚀刻抗性相对于所述Praäkursor。

公开(公告)号：WO2002069345A3

公开(公告)日：2002-09-06

申请号：PCT/DE2002/000436

申请日：2002-02-06

Applicant: INFINEON TECHNOLOGIES AG ,  SELL, Bernhard ,  SÄNGER, Annette ,  SCHUMANN, Dirk

Inventor： SELL, Bernhard ,  SÄNGER, Annette ,  SCHUMANN, Dirk

IPC: H01L21/8242

Abstract: Die vorliegende Erfindung betrifft ein neuartiges Verfahren zur Herstellung eines Speicherkondensators, welcher als Graben- oder Stapelkondensator ausgeführt ist und insbesondere in einer DRAM-Speicherzelle verwendet wird. Das erfindungsgemäße Verfahren umfaßt die Schritte zum Bilden einer unteren metallischen Kondensatorelektrode (13), eines Speicherdielektrikums (14) und einer oberen Kondensatorelektrode (15), wobei die untere metallische Kondensatorelektrode (13) in der Weise selbstjustiert auf einem Silizium-Grundmaterial (1) gebildet wird, daß zunächst freiliegende Silizium-Bereiche an den Stellen, an denen die untere Kondensatorelektrode zu bilden ist, erzeugt werden und sodann auf den freiliegenden Silizium-Bereichen Metallsilizid (13) selektiv gebildet wird.

公开(公告)号：WO02069345A2

公开(公告)日：2002-09-06

申请号：PCT/DE0200436

申请日：2002-02-06

Applicant: INFINEON TECHNOLOGIES AG ,  SELL BERNHARD ,  SAENGER ANNETTE ,  SCHUMANN DIRK

Inventor： SELL BERNHARD ,  SAENGER ANNETTE ,  SCHUMANN DIRK

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/316 ,  H01L21/8242 ,  H01L27/108 ,  G11C15/00

CPC classification number: H01L27/10861 ,  H01L21/28518 ,  H01L21/31604 ,  H01L27/10814 ,  H01L28/60

Abstract: The invention relates to a novel method for production of a memory capacitor, embodied as a trench or laminar condenser and is used, in particular, in a DRAM memory cell. Said method comprises the following steps: a lower metallic condenser electrode (13), a storage dielectric (14) and an upper condenser electrode (15) are formed, whereby the lower metallic condenser electrode (13) is formed in a self-justified manner on a silicon base material (1), then a free silicon region is formed in those positions where the lower condenser electrode is to be formed and then metal silicide (13) is formed selectively on the free silicon.

Abstract translation: 本发明涉及一种用于存储电容器，其被设计为沟槽或叠层电容器，特别是用于在DRAM的存储单元的制备的新方法。 本发明方法包括在上一个硅基底材料的自对准的方式形成下金属电容器电极（13），存储介质（14）和上电容器电极（15），所述下部金属电容器电极（13）的步骤（1）形成 是，首先在在该下电容器电极是该位置的所有暴露的硅区中形成，产生，然后施加到金属硅化物（13）的暴露的硅区域上选择性地形成。