公开(公告)号：WO2019055052A1

公开(公告)日：2019-03-21

申请号：PCT/US2017/052109

申请日：2017-09-18

Applicant: INTEL CORPORATION ,  GLASSMAN, Timothy E. ,  SEGHETE, Dragos ,  STRUTT, Nathan ,  ASURI, Namrata S. ,  GOLONZKA, Oleg

Inventor： GLASSMAN, Timothy E. ,  SEGHETE, Dragos ,  STRUTT, Nathan ,  ASURI, Namrata S. ,  GOLONZKA, Oleg

IPC: H01L45/00

Abstract: Approaches for fabricating RRAM stacks with reduced forming voltage, and the resulting structures and devices, are described. In an example, a resistive random access memory (RRAM) device includes a conductive interconnect in an inter-layer dielectric (ILD) layer above a substrate. An RRAM element is on the conductive interconnect, the RRAM element including a first electrode layer on the uppermost surface of the conductive interconnect. A resistance switching layer is on the first electrode layer, the resistance switching layer including a first metal oxide material layer on the first electrode layer, and a second metal oxide material layer on the first metal oxide material layer, the second metal oxide material layer including a metal species not included in the first metal oxide material layer. An oxygen exchange layer is on the second metal oxide material layer of the resistance switching layer. A second electrode layer is on the oxygen exchange layer.

公开(公告)号：WO2019005167A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040510

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  STRUTT, Nathan ,  WU, Stephen Y. ,  ASURI, Namrata S. ,  GLASSMAN, Timothy E. ,  GOLONZKA, Oleg ,  MUKHERJEE, Niloy ,  SEGHETE, Dragos ,  WIEGAND, Christopher J.

Inventor： STRUTT, Nathan ,  WU, Stephen Y. ,  ASURI, Namrata S. ,  GLASSMAN, Timothy E. ,  GOLONZKA, Oleg ,  MUKHERJEE, Niloy ,  SEGHETE, Dragos ,  WIEGAND, Christopher J.

IPC: H01L45/00

CPC classification number: H01L45/08 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: An approach for integrating a resistive random access memory (RRAM) device on a dual bottom electrode layer is described. In an example, a resistive random access memory (RRAM) device includes a dual bottom electrode disposed above a substrate. The dual bottom electrode includes a first conductive layer disposed above a substrate, a second conductive layer disposed above the first conductive layer and an intermediate layer between the first conductive layer and the second conductive layer, where the intermediate layer includes oxygen. A switching layer is disposed on the dual bottom electrode layer. An oxygen exchange layer is disposed on the switching layer and a top electrode is disposed on the switching layer.

公开(公告)号：WO2019005164A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040507

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  OGUZ, Kaan ,  O'BRIEN, Kevin P. ,  KUO, Charles C. ,  DOYLE, Brian S. ,  DOCZY, Mark L. ,  WIEGAND, Christopher J. ,  RAHMAN, Tofizur ,  OUELLETTE, Daniel G. ,  BROCKMAN, Justin S. ,  GHANI, Tahir ,  GOLONZKA, Oleg

Inventor： OGUZ, Kaan ,  O'BRIEN, Kevin P. ,  KUO, Charles C. ,  DOYLE, Brian S. ,  DOCZY, Mark L. ,  WIEGAND, Christopher J. ,  RAHMAN, Tofizur ,  OUELLETTE, Daniel G. ,  BROCKMAN, Justin S. ,  GHANI, Tahir ,  GOLONZKA, Oleg

IPC: H01L43/10 ,  H01L43/12

Abstract: A memory device includes a bottom electrode, a fixed magnet above the bottom electrode, a tunnel barrier on the fixed magnet, a free magnet on the tunnel barrier. One of the free magnet or the fixed magnet includes a magnetic alloy consisting of iron and boron, and one or more elements selected from the group consisting of Si, Ge, Al, Hf, W, Ru, Ir, Ta, Cr and Mo where the total amount of the one or more elements is less than or equal to 10 atomic percent of the total composition of the magnetic alloy. A memory device further includes an oxide layer on the free magnet, a follower magnetic layer on the oxide layer and a top electrode above the follower magnetic layer.

公开(公告)号：WO2015147875A1

公开(公告)日：2015-10-01

申请号：PCT/US2014/032240

申请日：2014-03-28

Applicant: INTEL CORPORATION ,  WIEGAND, Christopher, J. ,  RAHMAN, Md Tofizur ,  GOLONZKA, Oleg ,  JAHAGIRDAR, Anant, H. ,  LU, Mengcheng

Inventor： WIEGAND, Christopher, J. ,  RAHMAN, Md Tofizur ,  GOLONZKA, Oleg ,  JAHAGIRDAR, Anant, H. ,  LU, Mengcheng

IPC: G11C11/15

CPC classification number: H01L27/222 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Embodiments of the present disclosure describe techniques and configurations associated with modulation of magnetic properties through implantation. In one embodiment, a method includes providing a substrate having an integrated circuit (IC) structure disposed on the substrate, the IC structure including a magnetizable material, implanting at least a portion of the magnetizable material with a dopant and magnetizing the magnetizable material, wherein said magnetizing is inhibited in the implanted portion of the magnetizable material. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例描述了通过植入调制磁性能的技术和配置。 在一个实施例中，一种方法包括提供具有设置在基板上的集成电路（IC）结构的基板，该IC结构包括可磁化材料，用掺杂剂注入至少一部分可磁化材料并使可磁化材料磁化，其中 在可磁化材料的注入部分中抑制了磁化。 可以描述和/或要求保护其他实施例。

公开(公告)号：WO2019182589A1

公开(公告)日：2019-09-26

申请号：PCT/US2018/023632

申请日：2018-03-21

Applicant: INTEL CORPORATION ,  RAHMAN, Tofizur ,  WIEGAND, Christopher J. ,  BROCKMAN, Christopher ,  OUELLETTE, Daniel G. ,  ALZATE VINASCO, Juan G. ,  SMITH, Angeline K. ,  GOLONZKA, Oleg

Inventor： RAHMAN, Tofizur ,  WIEGAND, Christopher J. ,  BROCKMAN, Christopher ,  OUELLETTE, Daniel G. ,  ALZATE VINASCO, Juan G. ,  SMITH, Angeline K. ,  GOLONZKA, Oleg

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: A memory device comprises a perpendicular magnetic tunnel junction (PMTJ) stack disposed above a substrate. The PMTJ stack has a first free layer magnet, a reference fixed magnet, and a barrier material between the first free layer magnet and the reference fixed magnet. A material stack is on the PMTJ device, where the material stack comprises a first cap material, a second free layer magnet, and a perpendicular magnetic anisotropy (PMA) booster material to increase PMA of the PMTJ stack.

公开(公告)号：WO2013095548A1

公开(公告)日：2013-06-27

申请号：PCT/US2011/066989

申请日：2011-12-22

Applicant: INTEL CORPORATION ,  GOLONZKA, Oleg ,  SIVAKUMAR, Swaminathan ,  WALLACE, Charles, H. ,  GHANI, Tahir

Inventor： GOLONZKA, Oleg ,  SIVAKUMAR, Swaminathan ,  WALLACE, Charles, H. ,  GHANI, Tahir

IPC: H01L21/28 ,  H01L21/3205 ,  H01L29/78 ,  H01L21/336

CPC classification number: H01L21/76897 ,  H01L21/28008 ,  H01L21/30625 ,  H01L21/32 ,  H01L21/76805 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/0653 ,  H01L29/66545

Abstract: Gate aligned contacts and methods of forming gate aligned contacts are described. For example, a method of fabricating a semiconductor structure includes forming a plurality of gate structures above an active region formed above a substrate. The gate structures each include a gate dielectric layer, a gate electrode, and sidewall spacers. A plurality of contact plugs is formed, each contact plug formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. A plurality of contacts is formed, each contact formed directly between the sidewall spacers of two adjacent gate structures of the plurality of gate structures. The plurality of contacts and the plurality of gate structures are formed subsequent to forming the plurality of contact plugs.

Abstract translation: 描述门对齐的触点和形成栅极对准触点的方法。 例如，制造半导体结构的方法包括在形成在衬底上方的有源区上方形成多个栅极结构。 栅极结构各自包括栅极介电层，栅电极和侧壁间隔物。 形成多个接触插塞，每个接触插塞直接形成在多个门结构的两个相邻门结构的侧壁间隔件之间。 形成多个触点，每个触点直接形成在多个栅极结构的两个相邻栅极结构的侧壁间隔件之间。 在形成多个接触插塞之后形成多个触点和多个栅极结构。

公开(公告)号：WO2010002718A2

公开(公告)日：2010-01-07

申请号：PCT/US2009048764

申请日：2009-06-26

Applicant: INTEL CORP ,  SELL BERNHARD ,  GOLONZKA OLEG

Inventor： SELL BERNHARD ,  GOLONZKA OLEG

IPC: H01L21/28

CPC classification number: H01L23/535 ,  H01L21/28052 ,  H01L21/28123 ,  H01L21/76805 ,  H01L21/76889 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53257 ,  H01L23/53266 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/4175 ,  H01L29/4925 ,  H01L29/66666 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a structure comprising a first contact metal disposed on a source/drain contact of a substrate, and a second contact metal disposed on a top surface of the first contact metal, wherein the second contact metal is disposed within an IlD disposed on a top surface of a metal gate disposed on the substrate.

Abstract translation: 描述形成微电子器件的方法和相关结构。 这些方法可以包括形成包括设置在基板的源极/漏极接触件上的第一接触金属和设置在第一接触金属的顶表面上的第二接触金属的结构，其中第二接触金属设置在设置的IID内 在设置在基板上的金属栅极的顶面上。

公开(公告)号：WO2019005157A1

公开(公告)日：2019-01-03

申请号：PCT/US2017/040496

申请日：2017-06-30

Applicant: INTEL CORPORATION ,  WIEGAND, Christopher J. ,  RAHMAN, Tofizur ,  OUELLETTE, Daniel G. ,  SMITH, Angeline K. ,  BROCKMAN, Justin S. ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOCZY, Mark L. ,  DOYLE, Brian S. ,  GOLONZKA, Oleg ,  ALZATE VINASCO, Juan G.

Inventor： WIEGAND, Christopher J. ,  RAHMAN, Tofizur ,  OUELLETTE, Daniel G. ,  SMITH, Angeline K. ,  BROCKMAN, Justin S. ,  O'BRIEN, Kevin P. ,  OGUZ, Kaan ,  DOCZY, Mark L. ,  DOYLE, Brian S. ,  GOLONZKA, Oleg ,  ALZATE VINASCO, Juan G.

IPC: H01L43/10 ,  H01L43/08 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L27/228 ,  H01L43/10 ,  H01L43/12

Abstract: A memory device includes a bottom electrode disposed above a substrate, a fixed magnet disposed above the bottom electrode, a tunnel barrier including a magnesium oxide disposed on the fixed magnet, a free magnet on the tunnel barrier, a cap oxide layer disposed on the free magnet, a follower magnet disposed on the oxide layer and a metallic cap disposed on the follower magnet. The metallic cap includes a metal such as Hf, W and Ta and further includes a trace amounts of an inert gas. One or more conductive nano-channels extend from the metallic cap through the free magnet and into the oxide layer, where each of the one or more conductive nano-channels include the material of the metallic cap. The memory device further includes an etch stop layer disposed on the metallic cap and a top electrode disposed on the etch stop layer.

公开(公告)号：WO2018125248A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/069638

申请日：2016-12-31

Applicant: INTEL CORPORATION ,  MANIPATRUNI, Sasikanth ,  CHAWLA, Jasmeet S. ,  WIEGAND, Christopher J. ,  NIKONOV, Dmitri E. ,  GOLONZKA, Oleg ,  YOUNG, Ian A.

Inventor： MANIPATRUNI, Sasikanth ,  CHAWLA, Jasmeet S. ,  WIEGAND, Christopher J. ,  NIKONOV, Dmitri E. ,  GOLONZKA, Oleg ,  YOUNG, Ian A.

IPC: H01L43/10 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01F10/1936 ,  H01F10/3254 ,  H01F10/3272 ,  H01L27/222 ,  H01L43/10

Abstract: Embodiments are generally directed to Heusler alloy based magnetic tunnel junctions and refractory interconnects. An embodiment of an apparatus includes a magnetic tunnel junction (MTJ) stack of an MRAM (Magnetoresistive Random Access Memory), the MTJ stack including a free magnetic layer and a fixed magnetic later, wherein the magnetic tunnel junction stack including one or more Heusler alloys; and metal interconnects for the MRAM, wherein the metal interconnects include one or more refractory metals, Silicides or Germinides of Nickel or Cobalt, refractory Heusler alloy, or Silicides of Heusler alloy.

公开(公告)号：WO2013101219A1

公开(公告)日：2013-07-04

申请号：PCT/US2011/068218

申请日：2011-12-30

Applicant: INTEL CORPORATION ,  STEIGERWALD, Joseph ,  GHANI, Tahir ,  GOLONZKA, Oleg

Inventor： STEIGERWALD, Joseph ,  GHANI, Tahir ,  GOLONZKA, Oleg

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/0924 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0886 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A wrap-around source/drain trench contact structure is described. A plurality of semiconductor fins extend from a semiconductor substrate. A channel region is disposed in each fin between a pair of source/drain regions. An epitaxial semiconductor layer covers the top surface and sidewall surfaces of each fin over the source/drain regions, defining high aspect ratio gaps between adjacent fins. A pair of source/drain trench contacts are electrically coupled to the epitaxial semiconductor layers. The source/drain trench contacts comprise a conformal metal layer and a fill metal. The conformal metal layer conforms to the epitaxial semiconductor layers. The fill metal comprises a plug and a barrier layer, wherein the plug fills a contact trench formed above the fins and the conformal metal layer, and the barrier layer lines the plug to prevent interdiffusion of the conformal metal layer material and plug material.

Abstract translation: 描述了环绕的源极/漏极沟槽接触结构。 多个半导体鳍片从半导体衬底延伸。 沟道区域设置在每个鳍片之间的一对源极/漏极区域之间。 外延半导体层覆盖源极/漏极区域上的每个鳍的顶表面和侧壁表面，限定相邻鳍片之间的高纵横比间隙。 一对源/漏沟槽触点电耦合到外延半导体层。 源极/漏极沟槽触点包括保形金属层和填充金属。 保形金属层符合外延半导体层。 填充金属包括塞子和阻挡层，其中塞子填充形成在鳍片和保形金属层之上的接触沟槽，并且阻挡层对插塞进行引线以防止共形金属层材料和插塞材料的相互扩散。