公开(公告)号：WO2004046935A2

公开(公告)日：2004-06-03

申请号：PCT/IB2003/005209

申请日：2003-11-14

Applicant: PHILIPS INTELLECTUAL PROPERTY & STANDARDS GMBH ,  KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  BUHR, Wolfgang

Inventor： BUHR, Wolfgang

IPC: G06F12/14

CPC classification number: G06F21/79

Abstract: In order further to develop a circuit arrangement (100) for electronic data processing - having at least one non-volatile memory module (10) for storing data to be protected against unauthorized access by means of encryption or decryption; - having at least one memory module interface logic circuit (12) assigned to the memory module (10) -- for addressing the memory module (10) and -- for writing the data to the memory module (10) or -- for reading out the data from the memory module (10);- having at least one code R[ead]O[nly]M[emory] module (20) for storing and/or supplying at least one R[ead]O[nly]M[emory] code; and- having at least one code ROM module interface logic circuit (22) assigned to the code ROM module (20) -- for addressing the code ROM module (20) and -- for reading out the ROM code from the code ROM module (20) and an en-/decryption method based thereon in such a way that on the one hand the key code may be changed for different controller versions with different ROM codes and on the other hand the length of the key code is not limited, it is proposed that the data assigned to the memory module (10) be encrypted or decrypted by means of the ROM code supplied by the code ROM module (20).

Abstract translation: 为了进一步开发用于电子数据处理的电路装置（100） - 具有用于存储要被保护的数据的至少一个非易失性存储器模块（10），以防止通过加密或解密的未经授权的访问; - 具有分配给所述存储器模块（10）的至少一个存储器模块接口逻辑电路（12） - 用于寻址所述存储器模块（10）和 - 用于将所述数据写入所述存储器模块（10）或 - 用于读取 从存储器模块（10）中取出数据; - 具有至少一个代码R [e] O [nly] M [emory]模块（20），用于存储和/或提供至少一个R [ 代码; 以及具有分配给代码ROM模块（20）的至少一个代码ROM模块接口逻辑电路（22） - 用于对代码ROM模块（20）进行寻址和 - 从代码ROM模块（20）读出ROM代码 20）和基于此的解密/解密方法，一方面可以针对具有不同ROM代码的不同控制器版本改变密钥代码，另一方面，密钥代码的长度不受限制， 提出分配给存储器模块（10）的数据通过由代码ROM模块（20）提供的ROM代码进行加密或解密。

公开(公告)号：WO2004046927A1

公开(公告)日：2004-06-03

申请号：PCT/IB2003/005106

申请日：2003-11-10

Applicant: PHILIPS INTELLECTUAL PROPERTY & STANDARDS GMBH ,  KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  OSTERTUN, Soenke ,  WAGNER, Mathias ,  MÜLLER, Detlef ,  BUHR, Wolfgang ,  GARBE, Joachim, Christoph, Hans

Inventor： OSTERTUN, Soenke ,  WAGNER, Mathias ,  MÜLLER, Detlef ,  BUHR, Wolfgang ,  GARBE, Joachim, Christoph, Hans

IPC: G06F11/10

CPC classification number: G06F11/1008

Abstract: In order to develop an electronic memory component or memory module (100), having at least one memory cell area (10) in which physical states (P) representing regular data are mapped by means of at least one mapping function (A) that describes at least one error correction code, for example at least one Hamming code, and also a method of operating at least one electronic memory component or memory module (100) of the abovementioned type, such that on the one hand the error detection probability is considerably increased and on the other hand unwritten memory blocks can be reliably distinguished from memory blocks that have already been written to once before, it is proposed that at least one further physical state in the form of at least one exceptional or special state (L, S) in the error correction code can be detected, encoded and/or indicated by means of the mapping function (A).

Abstract translation: 为了开发具有至少一个存储单元区域（10）的电子存储器组件或存储器模块（100），其中通过至少一个映射功能（A）映射表示常规数据的物理状态（P） 至少一个纠错码，例如至少一个汉明码，以及操作上述类型的至少一个电子存储器组件或存储器模块（100）的方法，使得一方面，错误检测概率相当大 而另一方面，未写入的存储器块可以可靠地与已经被写入一次的存储器块区分开来，所以提出至少一种形式为至少一个异常或特殊状态的物理状态（L，S ）可以通过映射函数（A）进行检测，编码和/或指示。

公开(公告)号：WO2008023297A3

公开(公告)日：2008-02-28

申请号：PCT/IB2007/053094

申请日：2007-08-06

Applicant: NXP B.V. ,  BUHR, Wolfgang ,  MUELLER, Detlef

Inventor： BUHR, Wolfgang ,  MUELLER, Detlef

IPC: G11C29/00

Abstract: In order to further develop a circuit arrangement (100) as well as a method of processing data to be protected against unauthorized access by means of encryption or decryption, by means of which method the data are stored in at least two memory modules (10, 12) in such way that a flexible configuration of any memory parts as main memory or redundancy memory is enabled, it is proposed to provide at least one real-time configurable redundancy concept for the memory modules (10, 12), by which the data can be stored redundantly in physically separate memory modules (10, 12).

公开(公告)号：WO2008023297A2

公开(公告)日：2008-02-28

申请号：PCT/IB2007053094

申请日：2007-08-06

Applicant: NXP BV ,  BUHR WOLFGANG ,  MUELLER DETLEF

Inventor： BUHR WOLFGANG ,  MUELLER DETLEF

IPC: G06F11/20 ,  G06F21/77 ,  G06F21/79

CPC classification number: G11C7/24 ,  G06F11/167 ,  G06F12/1408 ,  G06F21/77 ,  G06F21/79 ,  G11C29/74

Abstract: In order to further develop a circuit arrangement (100) as well as a method of processing data to be protected against unauthorized access by means of encryption or decryption, by means of which method the data are stored in at least two memory modules (10, 12) in such way that a flexible configuration of any memory parts as main memory or redundancy memory is enabled, it is proposed to provide at least one real-time configurable redundancy concept for the memory modules (10, 12), by which the data can be stored redundantly in physically separate memory modules (10, 12).

Abstract translation: 为了进一步开发电路装置（100）以及通过加密或解密来处理要防止未授权访问的数据的方法，通过哪种方法将数据存储在至少两个存储器模块（10， 12），使得能够使得作为主存储器或冗余存储器的任何存储器部件的灵活配置得以启用，建议为存储器模块（10,12）提供至少一个实时可配置冗余概念，通过该存储器模块 可以冗余地存储在物理上分离的存储器模块（10,12）中。

公开(公告)号：WO03060721A2

公开(公告)日：2003-07-24

申请号：PCT/IB0205481

申请日：2002-12-12

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PHILIPS CORP INTELLECTUAL PTY ,  BUHR WOLFGANG ,  MUELLER DETLEF

Inventor： BUHR WOLFGANG ,  MUELLER DETLEF

IPC: G06F12/02 ,  G06F12/00 ,  G07F7/10

CPC classification number: G07F7/1008 ,  G06Q20/341 ,  G06Q20/3552 ,  G06Q20/35765

Abstract: The invention relates to a method and a system for writing NV memories in a controller architecture, in addition to a corresponding computer program product and a corresponding computer-readable storage medium, which can be used in particular to accelerate writing or programming operations in NV code memories of microcontrollers, such as e.g. smartcard controllers. The method consists of extending the instruction set of the controller by MOVCWR (move code write) instructions, which allow a defined data item (byte) to be written to a defined target address in an NV code memory. The data item (byte) is written to the correct position of the cache page register of the relevant NV memory and the page-address pointer register of the memory is updated with the corresponding page address. If an MMU (Memory Management Unit) is present, the MOVCWR write operation to the cache page register, in addition to the MOVC read or code fetch operation are controlled by said MMU.

Abstract translation: 本发明描述了一种方法和用于描述在控制器架构NV存储器，以及一个相应的计算机程序产品和相应的计算机可读存储介质，其可以特别用于写入或在微控制器的NV代码存储器编程操作的装置， 加快，例如智能卡控制器。 该过程包括在指令集控制器到所谓的的扩展。MOVCWR（移动代码写）指令，以及，其使得一个NV代码存储器内的在限定的目的地地址的定义的数据字（字节）写入。 数据字（字节）由此被写入到各自的非存储器的高速缓存页寄存器的正确位置，并更新与页面地址相关联的记忆页地址指针寄存器。 如果MMU（内存管理单元）时，该MOVCWR写发生在高速缓存页面注册怎么MOVC阅读或代码取，MMU的控制。

公开(公告)号：WO2002093387A2

公开(公告)日：2002-11-21

申请号：PCT/IB2002/001690

申请日：2002-05-15

Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V. ,  PHILIPS CORPORATE INTELLECTUAL PROPERTY GMBH ,  BUHR, Wolfgang

Inventor： BUHR, Wolfgang

IPC: G06F12/14

CPC classification number: G06F12/1408

Abstract: The invention relates to a method of dual-stage scrambling of addresses (LogAdr) with which a central processor (10) accesses a memory (13). A first encryption logic (11) applies a fixed, unchangeable key (KEY1), whereas a second encryption logic (12) applies a changeable second key (KEY2) stored in the memory (13). The configuration data written during the initialization phase of the central processor (10) are preferably stored in a special configuration range which is accessed via a bypass (15) while bypassing the second encryption logic (12). The bypass is activated by a bypass logic (14) which compares the addresses (Cipher1) encrypted in the first stage with values (SecRowCipher1, SecRowCipher2) stored during the initialization phase.

Abstract translation: 本发明涉及一种中央处理器（10）访问存储器（13）的地址（LogAdr）的双级加扰方法。 第一加密逻辑（11）应用固定的不可改变的密钥（KEY1），而第二加密逻辑（12）应用存储在存储器（13）中的可变的第二密钥（KEY2）。 在中央处理器（10）的初始化阶段期间写入的配置数据优选地存储在通过旁路（15）而被旁路的第二加密逻辑（12）中访问的特殊配置范围内。 旁路由旁路逻辑（14）激活，旁路逻辑（14）将第一级加密的地址（Cipher1）与初始化阶段期间存储的值（SecRowCipher1，SecRowCipher2）进行比较。

公开(公告)号：WO1994027277A1

公开(公告)日：1994-11-24

申请号：PCT/IB1994000092

申请日：1994-05-05

Applicant: PHILIPS PATENTVERWALTUNG GMBH ,  PHILIPS NORDEN AB ,  PHILIPS ELECTRONICS N.V. ,  BUHR, Wolfgang

Inventor： PHILIPS PATENTVERWALTUNG GMBH ,  PHILIPS NORDEN AB ,  PHILIPS ELECTRONICS N.V.

IPC: G09G05/08

CPC classification number: G09G5/08

Abstract: It is known to display a cursor field of variable magnitude notably for accentuating text segments on a display screen. No separate symbol is reproduced in this cursor field. On the other hand, it is also known to display a cursor symbol in a cursor field, where the areas of the cursor field outside the symbol are generally suppressed. The position of this field can be controlled, but the magnitude is always fixed. The shape of the cursor symbol is often stored in a random access memory so that it can be readily modified. For the display of also a cursor symbol of variable magnitude, the invention proposes to address the cursor memory by means of a separate addressing device which operates only during display of the cursor field. The organization of the memory for the cursor symbol, customarily constructed as a matrix memory, then becomes fully independent of the rows and columns of the cursor field, i.e. to the cursor symbol the memory appears as a pure linear memory. As a result, this memory can be utilized in a substantially improved manner and the display of even large cursor symbols requires only a limited storage capacity.

Abstract translation: 已知显示用于在显示屏幕上突出显示文本段的可变幅度的光标字段。 在此光标字段中不再现单独的符号。 另一方面，还已知在光标字段中显示光标符号，其中通常抑制符号外的光标字段的区域。 该场的位置可以被控制，但是幅度总是固定的。 光标符号的形状通常存储在随机存取存储器中，从而可以容易地进行修改。 为了显示可变大小的光标符号，本发明提出通过仅在光标字段的显示期间操作的单独的寻址装置来对光标存储器进行寻址。 通常构造为矩阵存储器的光标符号的存储器的组织然后变得完全独立于光标字段的行和列，即到存储器显示为纯线性存储器的光标符号。 结果，可以以显着改进的方式使用该存储器，并且甚至大的光标符号的显示仅需要有限的存储容量。

公开(公告)号：WO2009112963A3

公开(公告)日：2009-11-19

申请号：PCT/IB2009050774

申请日：2009-02-26

Applicant: NXP BV ,  BUHR WOLFGANG ,  ROSENBER BIRGER

Inventor： BUHR WOLFGANG ,  ROSENBER BIRGER

IPC: G06K19/07 ,  G06K7/00

CPC classification number: G06K7/0008 ,  G06K19/07

Abstract: The invention relates to an integrated circuit card (1) comprising: an input/output block (4) for receiving external command data from an interface device (2); a central processing unit (CPU) (3) in signal communication with the input/output block (4) for performing a task corresponding to the received command data; a judgement block (5) in signal communication with the central processing unit (3) for judging whether a working time of the central processing unit (3) reaches a reference time, after an input of the external command data is completed; and a control block (6) in signal communication with the judgement block (5) for operating responsive to an output of the judgement block, wherein the control block controls such that a S(WTX request) is output via the input/output block (4) without intervention by the central processing unit whenever the interface device (2) connected to the integrated circuit card (1) transmits a command to the integrated circuit card and the integrated circuit card is not able to respond to this command within the defined maximum waiting time.

Abstract translation: 本发明涉及一种集成电路卡（1），包括：用于从接口装置（2）接收外部命令数据的输入/输出块（4） 与所述输入/输出块（4）进行信号通信的用于执行与所接收的命令数据相对应的任务的中央处理单元（CPU）（3）; 在所述外部命令数据的输入完成之后，与所述中央处理单元（3）进行信号通信的判断块（5），用于判断所述中央处理单元（3）的工作时间是否到达基准时间; 以及控制块（6），其与所述判断块（5）进行信号通信，用于响应于所述判断块的输出进行操作，其中所述控制块进行控制，使得经由所述输入/输出块输出S（WTX请求） 4）当连接到集成电路卡（1）的接口设备（2）向集成电路卡发送命令并且集成电路卡不能在所定义的最大值内响应该命令时，无需中央处理单元的干预 等待的时间。

公开(公告)号：WO2004046935A3

公开(公告)日：2005-03-17

申请号：PCT/IB0305209

申请日：2003-11-14

Applicant: PHILIPS INTELLECTUAL PROPERTY ,  KONINKL PHILIPS ELECTRONICS NV ,  BUHR WOLFGANG

Inventor： BUHR WOLFGANG

IPC: G06F1/00 ,  G06F12/14 ,  G06F21/79 ,  H04L9/12

CPC classification number: G06F21/79

Abstract: In order further to develop a circuit arrangement (100) for electronic data processing - having at least one non-volatile memory module (10) for storing data to be protected against unauthorized access by means of encryption or decryption -having at least one code R`ead! O`nly!M`emory! module (20) for storing and/or supplying at least one R`ead!O`nly!M`emory! code; and -having at least one code ROM module interface logic circuit (22) assigned to the code ROM module (20) and an en-/decryption method based thereon in such a way that on the one hand the key code may be changed for different controller versions with different ROM codes and on the other hand the length of the key code is not limited, it is proposed that the data assigned to the memory module (10) be encrypted or decrypted by means of the ROM code supplied by the code ROM module (20).

Abstract translation: 为了进一步开发用于电子数据处理的电路装置（100） - 具有用于存储要被保护的数据的至少一个非易失性存储器模块（10），以防止未经授权的访问，借助于加密或解密 - 至少一个代码R `EAD！ O`nly！M`emory！ 模块（20），用于存储和/或提供至少一个R`ead！O`nly！M`emory！ 码; 以及分配给代码ROM模块（20）的至少一个代码ROM模块接口逻辑电路（22）和基于此的解密方法，使得一方面可以改变密钥代码以进行不同的 具有不同ROM代码的控制器版本，另一方面，密钥代码的长度不受限制，建议通过由代码ROM提供的ROM代码对分配给存储器模块（10）的数据进行加密或解密 模块（20）。

公开(公告)号：WO02093387A3

公开(公告)日：2003-01-30

申请号：PCT/IB0201690

申请日：2002-05-15

Applicant: KONINKL PHILIPS ELECTRONICS NV ,  PHILIPS CORP INTELLECTUAL PTY ,  BUHR WOLFGANG

Inventor： BUHR WOLFGANG

IPC: G06F12/14 ,  G06F21/24

CPC classification number: G06F12/1408

Abstract: The invention relates to a method of dual-stage scrambling of addresses (LogAdr) with which a central processor (10) accesses a memory (13). A first encryption logic (11) applies a fixed, unchangeable key (KEY1), whereas a second encryption logic (12) applies a changeable second key (KEY2) stored in the memory (13). The configuration data written during the initialization phase of the central processor (10) are preferably stored in a special configuration range which is accessed via a bypass (15) while bypassing the second encryption logic (12). The bypass is activated by a bypass logic (14) which compares the addresses (Cipher1) encrypted in the first stage with values (SecRowCipher1, SecRowCipher2) stored during the initialization phase.

Abstract translation: 本发明涉及一种中央处理器（10）访问存储器（13）的地址（LogAdr）的双级加扰方法。 第一加密逻辑（11）应用固定的不可改变的密钥（KEY1），而第二加密逻辑（12）应用存储在存储器（13）中的可变的第二密钥（KEY2）。 在中央处理器（10）的初始化阶段期间写入的配置数据优选地存储在通过旁路（15）而被旁路的第二加密逻辑（12）中访问的特殊配置范围内。 旁路由旁路逻辑（14）激活，旁路逻辑（14）将第一级加密的地址（Cipher1）与初始化阶段期间存储的值（SecRowCipher1，SecRowCipher2）进行比较。