公开(公告)号：WO1997024673A1

公开(公告)日：1997-07-10

申请号：PCT/US1996017108

申请日：1996-10-23

Applicant: MOTOROLA INC. ,  DWORKIN, James, Douglas ,  BUSS, John, Michael

Inventor： MOTOROLA INC.

IPC: G06F12/00

CPC classification number: G06F15/8015 ,  G06F9/3824

Abstract: A computing element (200) in a computational array includes a memory bypass system which performs in a single clock cycle a calculation that requires the result of a previous calculation performed in a previous clock cycle. The computing element has a computational unit (210) which performs calculations and a result memory (240) which stores the results of the calculations. The memory bypass method and system bypasses the result memory (240) when it determines that the result of a calculation is needed as an input to the next calculation to be performed, and provides the result of the calculation directly to the computational unit (210) to perform the next calculation. Otherwise, when the result is not needed as the input in the next calculation, the memory bypass method and system reads the input for the next calculation from the result memory (240).

Abstract translation: 计算阵列中的计算元件（200）包括存储器旁路系统，其在单个时钟周期中执行需要在先前时钟周期中进行的先前计算的结果的计算。 计算元件具有执行计算的计算单元（210）和存储计算结果的结果存储器（240）。 当存储器旁路方法和系统确定需要计算结果作为要执行的下一个计算的输入时，绕过结果存储器（240），并将计算结果直接提供给计算单元（210） 执行下一次计算。 否则，当不需要结果作为下一次计算中的输入时，存储器旁路方法和系统从结果存储器（240）读取下次计算的输入。

公开(公告)号：WO1996028774A1

公开(公告)日：1996-09-19

申请号：PCT/US1996000955

申请日：1996-01-29

Applicant: MOTOROLA INC. ,  BUSS, John, Michael ,  DWORKIN, James ,  LLOYD, Scott, Edward ,  PAN, Shao, Wei ,  SMITH, Stephen, L. ,  WANG, Shay-Ping, Thomas

Inventor： MOTOROLA INC.

IPC: G06F01/02

CPC classification number: G06F7/556

Abstract: A circuit and method for computing an exponential signal x is provided. The circuit includes a logarithm converter (4) which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts (8) the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register (28) shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter (34) converts the combined value to the exponential signal.

Abstract translation: 提供了一种用于计算指数信号x 的电路和方法。 电路包括将输入信号转换为表示输入信号x的对数的二进制字的对数转换器（4）。 第一移位寄存器以逐位方式移位（8）二进制字以产生第一中间值; 而第二移位寄存器（28）以逐位方式移位二进制字以产生第二中间值。 移位寄存器可以使用多路复用器来实现。 换档操作等效于将中间值乘以2的幂。 将第一中间值添加到第二中间值或从第二中间值中减去以产生组合值。 逆对数转换器（34）将组合值转换为指数信号。

公开(公告)号：WO1997024657A1

公开(公告)日：1997-07-10

申请号：PCT/US1996016982

申请日：1996-10-23

Applicant: MOTOROLA INC. ,  DWORKIN, James, Douglas ,  BUSS, John, Michael

Inventor： MOTOROLA INC.

IPC: G06F07/38

CPC classification number: G06F7/552 ,  G06F2207/5523

Abstract: A computational array (120) includes at least one computing element (130) that calculates multiple terms in a polynomial. The computing element (130) obtains an input value of each variable in each of the multiple terms and a subscript uniquely identifying the variable. The computing element (130) reads a term identifier and an exponent corresponding to the variable at a memory location based on the subscript. The computing element (130) multiplies the input value by a selected weight value and multiplies the input value by itself a number of times based on the exponent and stores the result at a memory location corresponding to the term identifier. The computing element (130) calculates multiple terms by distinguishing each of the terms with the term identifier.

Abstract translation: 计算阵列（120）包括计算多项式中的多个项的至少一个计算元件（130）。 计算元件（130）获得多个项中的每一个中的每个变量的输入值，以及唯一地标识该变量的下标。 计算元件（130）基于下标在存储器位置读取对应于变量的术语标识符和指数。 计算元件（130）将输入值乘以所选择的权重值，并且基于指数将输入值本身乘以多次，并将结果存储在与术语标识符相对应的存储器位置处。 计算元件（130）通过将每个术语与术语标识符区分开来计算多个术语。

公开(公告)号：WO1996024096A1

公开(公告)日：1996-08-08

申请号：PCT/US1996000145

申请日：1996-01-03

Applicant: MOTOROLA INC. ,  DWORKIN, James, Douglas ,  BUSS, John, Michael

Inventor： MOTOROLA INC.

IPC: G06F07/00

CPC classification number: G06F7/556 ,  G06F1/0307 ,  H03M7/50

Abstract: A converter which may be used for implementing either logarithmic or inverse-logarithmic functions is disclosed. The converter includes a memory (22), two multipliers (28 and 30), and two adders (32 and 34). The memory (22) stores a plurality of coefficients which are based on a second-order Taylor polynomial used to estimate a logarithmic or inverse-logarithmic function over a domain of input values. A method of using the converter is also disclosed.

Abstract translation: 公开了可用于实现对数或反对数函数的转换器。 转换器包括存储器（22），两个乘法器（28和30）和两个加法器（32和34）。 存储器（22）存储多个系数，其基于用于估计输入值的域上的对数或反对数函数的二阶泰勒多项式。 还公开了一种使用该转​​换器的方法。