Abstract:
A computing element (200) in a computational array includes a memory bypass system which performs in a single clock cycle a calculation that requires the result of a previous calculation performed in a previous clock cycle. The computing element has a computational unit (210) which performs calculations and a result memory (240) which stores the results of the calculations. The memory bypass method and system bypasses the result memory (240) when it determines that the result of a calculation is needed as an input to the next calculation to be performed, and provides the result of the calculation directly to the computational unit (210) to perform the next calculation. Otherwise, when the result is not needed as the input in the next calculation, the memory bypass method and system reads the input for the next calculation from the result memory (240).
Abstract:
A computational array (120) includes at least one computing element (130) that calculates multiple terms in a polynomial. The computing element (130) obtains an input value of each variable in each of the multiple terms and a subscript uniquely identifying the variable. The computing element (130) reads a term identifier and an exponent corresponding to the variable at a memory location based on the subscript. The computing element (130) multiplies the input value by a selected weight value and multiplies the input value by itself a number of times based on the exponent and stores the result at a memory location corresponding to the term identifier. The computing element (130) calculates multiple terms by distinguishing each of the terms with the term identifier.
Abstract:
A converter which may be used for implementing either logarithmic or inverse-logarithmic functions is disclosed. The converter includes a memory (22), two multipliers (28 and 30), and two adders (32 and 34). The memory (22) stores a plurality of coefficients which are based on a second-order Taylor polynomial used to estimate a logarithmic or inverse-logarithmic function over a domain of input values. A method of using the converter is also disclosed.
Abstract:
A converter which may be used for implementing either logarithmic or inverse-logarithmic functions includes a memory (20), a multiplier (22), and an adder (38). The memory (20) stores a plurality of pre-computed values which are used in an interpolation to estimate a logarithmic or inverse-logarithmic function over a domain of input signals.
Abstract:
A floating point conversion circuit (10) converts a fixed point data signal having a fixed point data format (200) to a floating point data signal having a floating point data format (300). The floating point conversion circuit (10) contains a twos complement circuit (110) and a programmable logic array (120) which determines the magnitude of the fixed point data signal and produces an exponent signal and a shift signal based on the magnitude determined. The floating point conversion circuit (10) also contains a barrel shifter (130) which shifts the fixed point data signal to adjust the magnitude based on the shift signal and thus produces a signal. The floating point conversion circuit (10) outputs a floating point data signal having a floating point exponent portion (320) represented by the exponent signal and a floating point portion (330) represented by the signal.
Abstract:
A circuit and method for computing an exponential signal x is provided. The circuit includes a logarithm converter (4) which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts (8) the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register (28) shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter (34) converts the combined value to the exponential signal.
Abstract:
A method for monitoring the performance of a catalytic converter (34) computes the oxygen storage capacity and desorption capacity of a catalyst within the catalytic converter (34). An engine control unit (10) receives mass flow rate information of air from a mass air flow rate sensor (12) and an injector driver (24), and receives electrical signals from an upstream exhaust gas sensor (28) and a downstream exhaust gas sensor (30). The engine control unit (10) calculates normalized air fuel ratios for the exhaust gas entering and leaving the catalytic converter (34) and performs numerical integration to determine the oxygen storage capacity and oxygen desorption capacity of the catalyst in the catalytic converter (34). The calculated oxygen storage and desorption capacities of the catalyst are compared with threshold values to determine the performance of the catalytic converter (34).
Abstract:
A low current drain switch interface circuit includes an input terminal (105), coupled to a first terminal (201) of a diode (204). A voltage follower circuit (211) is coupled to a second terminal (203) of the diode (204). A current source (215) is coupled between an output terminal (213) of the voltage follower circuit (211) and a power supply terminal (111). A mechanical switch (101) is coupled to the input terminal (105). The voltage follower circuit (211) outputs a voltage (119) indicative of a physical state of the mechanical switch (101).
Abstract:
A multichannel selective call receiver (10) with a receiver (11), a controller (16), a baud detector (17) and a memory (18). Controller (16) is adapted to control receiver (11) in receiving information on a channel (14). The information on channel (14) includes mandatory frames having information fields. If the information fields in a mandatory frame on channel (14) does not indicate more information for multichannel selective call receiver (10) in the rest of the mandatory frame, then controller (16) controls receiver (11) to receive information on other channels (15) during the rest of the mandatory frame. The information on channel (14) and other channels (15) are processed in accordance with channel pririty as indicated in a channel list stored in memory (18).
Abstract:
The present invention provides a method of assigning a unique device identification to an electronic device (28, 30, 32, 34) coupled into a communication architecture. Once coupled into the communication architecture a piece of globally unique identifying data is retrieved and utilized to generate a device identification which identification is then assigned to the device (28, 30, 32, 34).