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    POWER SOURCE AND METHOD OF MANAGING A POWER SOURCE
    1.
    发明申请
    POWER SOURCE AND METHOD OF MANAGING A POWER SOURCE 审中-公开
    电源和管理电源的方法

    公开(公告)号：WO2009048974A1

    公开(公告)日：2009-04-16

    申请号：PCT/US2008/079234

    申请日：2008-10-08

    Applicant: HUM CYCLES, INC. ,  CABOT, Mason ,  DEUTH, Forrest

    Inventor： CABOT, Mason ,  DEUTH, Forrest

    IPC: H01M10/42

    CPC classification number: H01M10/4207 ,  H01M10/052 ,  H01M10/425 ,  H01M10/482

    Abstract: In one embodiment, the invention includes a power source having a plurality of battery groups and a processor coupled to the groups and adapted to electrically disconnect a group from the power source. Each group includes a plurality of cells, a sensor adapted to sense operating parameters of the cells, and a protection circuit coupled to the sensor. In another embodiment, the invention includes a method of managing a power source with a two-tier approach. On a group level, the method includes retrieving cell data representative of the operating parameters of the cells of the group and managing the connection state of the group based on the retrieved cell data. On a system level, the method includes, retrieving group data representative of the operating parameters of the groups and managing the connection state of the group based on the retrieved group data.

    Abstract translation: 在一个实施例中，本发明包括具有多个电池组的电源和耦合到组的处理器，并且适于将组与电源电断开。 每个组包括多个单元，适于感测单元的运行参数的传感器以及耦合到该传感器的保护电路。 在另一个实施例中，本发明包括一种使用两层方法来管理电源的方法。 在组级别上，该方法包括：检索表示组的小区的运行参数的小区数据，并根据检索到的小区数据来管理组的连接状态。 在系统级别，该方法包括：检索表示组的操作参数的组数据，并且基于检索到的组数据来管理组的连接状态。

    METHOD FOR PROGRAMMER-CONTROLLED CACHE LINE EVICTION POLICY
    2.
    发明申请
    METHOD FOR PROGRAMMER-CONTROLLED CACHE LINE EVICTION POLICY 审中-公开
    编程控制缓存线路故障排除策略的方法

    公开(公告)号：WO2006071792A3

    公开(公告)日：2007-01-04

    申请号：PCT/US2005046846

    申请日：2005-12-20

    Applicant: INTEL CORP ,  CABOT MASON

    Inventor： CABOT MASON

    IPC: G06F12/12 ,  G06F9/45

    CPC classification number: G06F12/126 ,  G06F12/121

    Abstract: A method and apparatus to enable programmatic control of cache line eviction policies. A mechanism is provided that enables programmers to mark portions of code with different cache priority levels based on anticipated or measured access patterns for those code portions. Corresponding cues to assist in effecting the cache eviction policies associated with given priority levels are embedded in machine code generated from source-and/or assembly-level code. Cache architectures are provided that partition cache space into multiple pools, each pool being assigned a different priority. In response to execution of a memory access instruction, an appropriate cache pool is selected and searched based on information contained in the instruction's cue. On a cache miss, a cache line is selected from that pool to be evicted using a cache eviction policy associated with the pool. Implementations of the mechanism or described for both n-way set associative caches and fully-associative caches.

    Abstract translation: 一种能够对高速缓存行驱逐策略进行编程控制的方法和装置。 提供了一种机制，其使得程序员能够基于对于这些代码部分的预期或测量的访问模式来标记具有不同高速缓存优先级的代码的部分。 有助于实现与给定优先级相关联的缓存驱逐策略的相应提示被嵌入在从源代码和/或汇编级代码生成的机器代码中。 提供了缓存体系结构，将缓存空间分成多个池，每个池被分配不同的优先级。 响应于存储器访问指令的执行，基于指令的提示中包含的信息来选择和搜索适当的高速缓存池。 在缓存未命中时，使用与该池相关联的缓存驱逐策略从该池中选择要被逐出的高速缓存行。 该机制的实施或描述为n路组合关联缓存和全关联缓存。

    METHOD FOR MANAGING A MODULAR POWER SOURCE
    4.
    发明申请
    METHOD FOR MANAGING A MODULAR POWER SOURCE 审中-公开
    用于管理模块化电源的方法

    公开(公告)号：WO2009121014A1

    公开(公告)日：2009-10-01

    申请号：PCT/US2009/038657

    申请日：2009-03-27

    Applicant: MISSION MOTOR COMPANY ,  CABOT, Mason ,  DURKEE, Paul ,  SHERWOOD, Mark

    Inventor： CABOT, Mason ,  DURKEE, Paul ,  SHERWOOD, Mark

    IPC: H02J3/12

    CPC classification number: H02J7/0026 ,  H02J7/0014 ,  Y02T10/7055

    Abstract: Disclosed is a method for management of a modular power source including the steps of setting a first operation threshold, selecting a module 10, retrieving data representative of the operating condition of the module 10, retrieving data representative of the time, storing the newly retrieved data, comparing the newly retrieved data to historical data representative of historical operating conditions of the module 10, determining a second operation threshold for the module 10 relative to the comparison, applying the second operation threshold for the module 10, and selecting the next module 10.

    Abstract translation: 公开了一种用于管理模块化电源的方法，包括以下步骤：设置第一操作阈值，选择模块10，检索表示模块10的操作条件的数据，检索表示时间的数据，存储新检索的数据 将新检索的数据与代表模块10的历史操作条件的历史数据进行比较，确定模块10相对于比较的第二操作阈值，应用模块10的第二操作阈值，并选择下一个模块10。

    METHOD FOR PROGRAMMER-CONTROLLED CACHE LINE EVICTION POLICY
    5.
    发明申请
    METHOD FOR PROGRAMMER-CONTROLLED CACHE LINE EVICTION POLICY 审中-公开
    编程控制缓存线路故障排除策略的方法

    公开(公告)号：WO2006071792A2

    公开(公告)日：2006-07-06

    申请号：PCT/US2005/046846

    申请日：2005-12-20

    Applicant: INTEL CORPORATION ,  CABOT, Mason

    Inventor： CABOT, Mason

    IPC: G06F12/12 ,  G06F9/45

    CPC classification number: G06F12/126 ,  G06F12/121

    Abstract: A method and apparatus to enable programmatic control of cache line eviction policies. A mechanism is provided that enables programmers to mark portions of code with different cache priority levels based on anticipated or measured access patterns for those code portions. Corresponding cues to assist in effecting the cache eviction policies associated with given priority levels are embedded in machine code generated from source-and/or assembly-level code. Cache architectures are provided that partition cache space into multiple pools, each pool being assigned a different priority. In response to execution of a memory access instruction, an appropriate cache pool is selected and searched based on information contained in the instruction's cue. On a cache miss, a cache line is selected from that pool to be evicted using a cache eviction policy associated with the pool. Implementations of the mechanism or described for both n-way set associative caches and fully-associative caches.

    Abstract translation: 一种能够对高速缓存行驱逐策略进行编程控制的方法和装置。 提供了一种机制，其使得程序员能够基于对于这些代码部分的预期或测量的访问模式来标记具有不同高速缓存优先级的代码的部分。 有助于实现与给定优先级相关联的缓存驱逐策略的相应提示被嵌入在从源代码和/或汇编级代码生成的机器代码中。 提供了缓存体系结构，将缓存空间分成多个池，每个池被分配不同的优先级。 响应于执行存储器访问指令，基于指令的提示中包含的信息来选择和搜索适当的高速缓存池。 在缓存未命中时，使用与该池相关联的缓存驱逐策略从该池中选择要被逐出的高速缓存行。 该机制的实施或描述为n路组合关联缓存和全关联缓存。

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