Abstract:
A virtual fabrication environment for semiconductor device structure development is discussed. The insertion of a multi-etch process step using material-specific behavioral parameters into a process sequence enables a multi-physics, multi- material etching process to be simulated using a suitable numerical technique. The multi-etch process step accurately and realistically captures a wide range of etch behavior and geometry to provide in a virtual fabrication system a semi-physical approach to modeling multi-material etches based on a small set of input parameters that characterize the etch behavior.
Abstract:
A virtual fabrication environment that enables 3D Design Rule Checks (DRCs) or Optical Rule Checks (ORCs) on 3D structural models of semiconductor devices to be performed is discussed. The virtual fabrication environment may perform 3D design rule checks, such as minimum line width, minimum space between features, and minimum contact area between adjacent materials, directly in 3D without making assumptions about the translation from 2D design data to a 3D structure effected by an integrated process flow for semiconductor devices. The required number of 3D design rule checks may therefore be significantly reduced from the number of design rule checks required in 2D environments. Embodiments may also perform the 3D design rule checks for a range of statistical variations in process and design parameters.
Abstract:
A method of numerically exploiting symmetry in a coupled electromechanical analysis, while still preserving the previously established advantages of the hybrid BEM/FEM approach for performing such analyses without exploiting symmetry is disclosed. The present invention allows advantageous acceleration techniques, which maximize analytical efficiency, to be employed for the analysis of systems with moving or deformable parts. The illustrative embodiment of the present invention is particularly applicable to simulating the physical behavior of MEMS (microelectromechanical system) devices and other complicated multi-domain devices.
Abstract:
A virtual fabrication environment for semiconductor device fabrication that includes an analytics module for determining specification limits using a fitting algorithm for non-normally distributed virtual metrology data is discussed.
Abstract:
Systems and methods for multi-material mesh generation from fill-fraction voxel model data are discussed. Voxel representations of model data are used to generate robust and accurate multi-material meshes. More particularly, a mesh generation pipeline in a virtual fabrication environment is described that robustly generates high-quality triangle surface and tetrahedral volume meshes from multi-material fill- fraction voxel data. Multi- material topology is accurately captured while preserving characteristic feature edges of the model.
Abstract:
Modeling of electrical behavior during the virtual fabrication of a semiconductor device structure is discussed. Electrical behavior occurring in a designated region of a semiconductor device structure may be determined during the virtual fabrication process. For example, resistance or capacitance values may be determined within a modeling domain of interest.
Abstract:
Micro-Electro-Mechanical System (MEMS) Variable Capacitor Apparatus and Related Methods. According to one embodiment, a MEMS variable capacitor is provided. The variable capacitor can include first and second electrodes being spaced apart, and at least one of the electrodes being movable when a voltage is applied across the first and second electrodes. The variable capacitor can also include a first conductive plate attached to and electrically isolated from the first electrode. Furthermore, the variable capacitor can include a second conductive plate attached to the second electrode and spaced from the first conductive plate for movement of at least one of the plates with respect to the other plate upon application of voltage across the first and second electrodes to change the capacitance between the first and second plates.
Abstract:
The invention relates to a method of high throughput chemical analysis comprising the steps of combining one test compound with a solution comprising m enzyme(s) and n substrate(s), wherein m is an integer equal to one or greater, n is an integer equal to one or greater, and m + n ≥ 3, incubating for a period of time said test compound within said solution, separating the chemical species in said combined solution by a chromatography step after said incubating step, and measuring the relative amounts of substrates and separately identifiable products produced therefrom by a chemical reaction catalyzed by said enzymes. The present SMSBEA assays are particularly well suited to enzyme-substrate systems in which both the substrate(s) and product(s) have mobilities such that they can be separated on short chromatography columns. The method of the invention is also particularly well suited to HTS applications in which an enzyme agonist or antagonist is sought. An advantage of the method is that the effects of a test compound on several enzymes may be analyzed simultaneously and without substantial purification of the enzyme solution, e.g., whole cell lysates.
Abstract:
A fluid interface port (15) in a separation device for separating a sample into different components is provided. The separation device includes an array of separation channels (500) and the fluid interface port (17) comprises an opening formed in the side wall of a separation channel (500) sized and dimensioned to form a virtual wall (15) when the separation channel is filled with a separation medium (20). The fluid interface port (17) is utilized to introduce a liquid sample (19a) into the separation medium (20). The interface ports (17) formed in the array of separation channels (500) are organized into one or more sample injectors. A cathode reservoir is multiplexed with one or more separation channels. To complete an electrical path, an anode reservoir which is common to some or all separation channels (500) is also provided.
Abstract:
Systems and methods for performing hole profile modeling in a semiconductor device virtual fabrication environment are discussed. More particularly, hole profiling modeling may be performed for complicated holes used in fabricating semiconductor devices to support DOEs to optimize the fabrication process.