公开(公告)号：WO2018125092A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/068938

申请日：2016-12-28

Applicant: INTEL CORPORATION

Inventor： SCHENKER, Richard E.

IPC: H01L21/768

CPC classification number: H01L21/76816 ,  H01L21/76801

Abstract: An integrated circuit die including a tight pitch interconnect structure and a method of fabricating a tight pitch interconnect structure is disclosed. The integrated circuit die includes a device layer and an interconnect structure. The interconnect structure includes a via to electrically couple with the device layer to a conductive layer. The interconnect structure includes a plurality of first features having a repeating pattern of feature sizes. The plurality of first features are disposed between a respective one of a plurality of second features. Each of the plurality of first features has a narrower width than the plurality of second features.

公开(公告)号：WO2017204821A1

公开(公告)日：2017-11-30

申请号：PCT/US2016/034624

申请日：2016-05-27

Applicant: INTEL CORPORATION

Inventor： LIN, Kevin ,  BRISTOL, Robert L. ,  SCHENKER, Richard E.

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76837 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/528

Abstract: Subtractive plug and tab patterning with photobuckets for back end of line (BEOL) spacer-based interconnects is described. In an example, a back end of line (BEOL) metallization layer for a semiconductor structure includes an inter-layer dielectric (ILD) layer disposed above a substrate. A plurality of conductive lines is disposed in the ILD layer along a first direction. A conductive tab is disposed in the ILD layer, the conductive tab coupling two of the plurality of conductive lines along a second direction orthogonal to the first direction. A conductive via is coupled to one of the plurality of conductive lines, the conductive via having a via hardmask thereon. An uppermost surface of each of the ILD layer, the plurality of conductive lines, the conductive tab, and the via hardmask is planar with one another.

Abstract translation: 描述了用于后端行线（BEOL）间隔件互连的带有光桶的减薄插塞和标签图案化。 在一个实例中，用于半导体结构的线后端（BEOL）金属化层包括设置在衬底上方的层间电介质（ILD）层。 多个导线沿着第一方向设置在ILD层中。 导电接片布置在ILD层中，导电接片沿着与第一方向正交的第二方向耦合多条导线中的两条导线。 导电通孔耦合到多个导电线中的一个，导电通孔上具有通孔硬掩模。 ILD层，多个导电线，导电接线片和通孔硬掩模中的每一个的最上表面彼此是平面的。

公开(公告)号：WO2017136577A1

公开(公告)日：2017-08-10

申请号：PCT/US2017/016253

申请日：2017-02-02

Applicant: TOKYO ELECTRON LIMITED ,  TOKYO ELECTRON U.S. HOLDINGS, INC.

Inventor： SMITH, Jeffrey ,  DEVILLIERS, Anton J.

IPC: H01L21/768 ,  H01L21/3205

CPC classification number: H01L21/76897 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/76801 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76883

Abstract: Techniques herein include methods of patterning substrates such as for back end of line (BEOL) metallization processes. Techniques herein enable fully self-aligned vias and lines. Processes herein include using selective deposition, protective films and combination etch masks for accurately patterning a substrate. In a substrate having uncovered portions of metal material and dielectric material, the dielectric material is grown upwardly without covering metal material. This raised dielectric material is conformally protected and used in subsequent patterning step to align via and line placement. Such combinations mitigate overlay errors.

Abstract translation: 这里的技术包括图案化衬底的方法，例如用于后端线（BEOL）金属化工艺。 这里的技术使完全自对准的过孔和线路成为可能。 本文的工艺包括使用选择性沉积，保护膜和组合蚀刻掩模来精确地图案化衬底。 在具有金属材料和介电材料的未覆盖部分的基板中，介电材料向上生长而不覆盖金属材料。 这种凸起的介电材料被保形地保护并用于随后的图案化步骤中以对齐通孔和线路放置。 这样的组合减轻了重叠错误。

公开(公告)号：WO2017105445A1

公开(公告)日：2017-06-22

申请号：PCT/US2015/066172

申请日：2015-12-16

Applicant: INTEL CORPORATION

Inventor： GULER, Leonard P.

IPC: H01L21/60 ,  H01L21/033

CPC classification number: H01L21/76834 ,  H01L21/76811 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/528 ,  H01L24/16 ,  H01L24/24 ,  H01L2224/16225 ,  H01L2224/24137 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2224/13099

Abstract: Grid self-aligned metal via processing schemes for back end of line (BEOL) interconnects are described. In an example, a method of fabricating an interconnect structure for a semiconductor die includes forming a lower metallization layer including alternating metal lines and dielectric lines above a substrate, the dielectric lines raised above the metal lines. A hardmask layer is formed on the metal lines of the lower metallization layer, between and co-planar with the dielectric lines of the lower metallization layer. A grating structure is formed above and orthogonal to the alternating metal lines and dielectric lines of the lower metallization layer. A mask is formed above the grating structure. Select regions of the hardmask layer are removed to expose select regions of the metal lines of the lower metallization layer. Metal vias are formed on the select regions of the metal lines of the lower metallization layer.

Abstract translation: 描述了用于后端线路（BEOL）互连的网格自对准金属通孔处理方案。 在一个示例中，一种制造用于半导体管芯的互连结构的方法包括：在衬底上方形成包括交替的金属线和电介质线的下金属化层，所述电介质线位于金属线上方。 硬掩模层形成在下金属化层的金属线上，在下金属化层的电介质线之间并与其共面。 光栅结构形成在下部金属化层的交替金属线和电介质线的上方并与其正交。 在光栅结构上方形成掩模。 选择硬掩模层的选择区域以暴露下金属化层的金属线的选定区域。 金属通孔形成在下金属化层的金属线的选定区域上。

公开(公告)号：WO2017059056A1

公开(公告)日：2017-04-06

申请号：PCT/US2016/054416

申请日：2016-09-29

Applicant: MEMS DRIVE, INC.

Inventor： GUTIERREZ, Roman ,  TANG, Tony ,  LIU, Xiaolei ,  WANG, Guiqin ,  NG, Matthew

IPC: B81B7/04 ,  B81B5/00 ,  B81B3/00

CPC classification number: H01L21/76816 ,  B81B3/0045 ,  B81B7/0029 ,  B81B2203/0353 ,  B81C1/00674 ,  B81C1/00682 ,  B81C2201/0112 ,  B81C2201/0135 ,  H01L21/768 ,  H01L21/76898 ,  H01L23/485 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/181

Abstract: A system and method for manipulating the structural characteristics of a MEMS device including etching a plurality of holes into the surface of a MEMS device, wherein the plurality of holes comprise one or more geometric shapes determined to provide specific structrual characteristics desired in the MEMS device.

Abstract translation: 一种用于操纵MEMS器件的结构特性的系统和方法，包括将多个孔蚀刻到MEMS器件的表面中，其中所述多个孔包括被确定为提供MEMS器件中期望的特定结构特征的一个或多个几何形状。

公开(公告)号：WO2017027130A1

公开(公告)日：2017-02-16

申请号：PCT/US2016/041163

申请日：2016-07-06

Applicant: INTEL CORPORATION

Inventor： ZHOU, Zheng ,  SCHUCKMAN, Amanda E. ,  BOYAPATI, Sri Ranga Sai

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/486 ,  H01L21/76804 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/145 ,  H01L23/49822 ,  H01L23/49827

Abstract: Embodiments herein may relate to a technique for generating a via in a substrate. Specifically, the technique may include coupling a polyethylene terephthalate (PET) layer, a protective metal layer, and a build-up layer to a metal layer. The process may further include etching a via in the PET layer, the protective metal layer, and at least a portion of the build-up layer. The process may further include performing a plasma desmear process on the substrate and then peeling the PET layer to remove the PET layer and the protective metal layer. Other embodiments may be described and/or claimed.

Abstract translation: 本文的实施例可以涉及用于在衬底中产生通孔的技术。 具体地，该技术可以包括将聚对苯二甲酸乙二醇酯（PET）层，保护金属层和堆积层耦合到金属层。 该方法还可以包括在PET层，保护性金属层和至少一部分积聚层中蚀刻通孔。 该方法还可以包括在衬底上执行等离子体去污工艺，然后剥离PET层以除去PET层和保护金属层。 可以描述和/或要求保护其他实施例。

公开(公告)号：WO2016209293A1

公开(公告)日：2016-12-29

申请号：PCT/US2015/038145

申请日：2015-06-26

Applicant: INTEL CORPORATION ,  LIN, Kevin ,  BRISTOL, Robert Lindsey ,  MYERS, Alan M.

Inventor： LIN, Kevin ,  BRISTOL, Robert Lindsey ,  MYERS, Alan M.

IPC: H01L21/027

CPC classification number: H01L21/32139 ,  H01L21/0334 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226

Abstract: Embodiments of the invention include methods of forming a textile patterned hardmask. In an embodiment, a first hardmask and a second hardmask are formed over a top surface of an interconnect layer in an alternating pattern. A sacrificial cross-grating may then be formed over the first and second hardmaskS. In an embodiment, portions of the first hardmask that are not covered by the sacrificial cross-grating are removed to form first openings and a third hardmask is disposed into the first openings. Embodiments may then include etching through portions of the second hardmask that are not covered by the sacrificial cross-grating to form second openings. The second openings may be filled with a fourth hardmask. According to an embodiment, the first, second, third, and fourth hardmasks are etch selective to each other. In an embodiment the sacrificial cross-grating may then be removed.

Abstract translation: 本发明的实施例包括形成织物图案化硬掩模的方法。 在一个实施例中，第一硬掩模和第二硬掩模以交替图案形成在互连层的顶表面上。 然后可以在第一和第二硬掩模S上形成牺牲交叉光栅。 在一个实施例中，去除未被牺牲交叉光栅覆盖的第一硬掩模的部分以形成第一开口，并且将第三硬掩模设置在第一开口中。 实施例可以包括蚀刻通过未被牺牲交叉光栅覆盖的第二硬掩模的部分以形成第二开口。 第二开口可以填充第四硬掩模。 根据实施例，第一，第二，第三和第四硬掩模是相互蚀刻选择性的。 在一个实施例中，可以去除牺牲交叉光栅。

公开(公告)号：WO2016209246A1

公开(公告)日：2016-12-29

申请号：PCT/US2015/037835

申请日：2015-06-25

Applicant: INTEL CORPORATION ,  SINGH, Kanwal Jit ,  LIN, Kevin ,  BRISTOL, Robert Lindsey

Inventor： SINGH, Kanwal Jit ,  LIN, Kevin ,  BRISTOL, Robert Lindsey

IPC: H01L21/764 ,  H01L27/108

CPC classification number: H01L23/53295 ,  H01L21/764 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/49827 ,  H01L23/5222 ,  H01L23/5226

Abstract: Embodiments of the invention include interconnect layers with floating interconnect lines and methods of forming such interconnect layers. In an embodiment, a plurality of openings are formed in a first sacrificial material layer. Conductive vias and dielectric pillars may be formed in the openings. A second sacrificial material layer may then be formed over the pillars, the vias, and the first sacrificial material layer. In an embodiment, a permeable etchstop layer is formed over a top surface of the second sacrificial layer. Embodiments then include forming an interconnect line in the second sacrificial material layer. In an embodiment, the first and second sacrificial material layers are removed through the permeable etchstop layer after the interconnect line has been formed. According to an embodiment, the permeable etchstop layer may then be stuffed with a fill material in order to harden the permeable etchstop layer.

Abstract translation: 本发明的实施例包括具有浮动互连线的互连层和形成这种互连层的方法。 在一个实施例中，在第一牺牲材料层中形成多个开口。 可以在开口中形成导电孔和电介质柱。 然后可以在柱，通孔和第一牺牲材料层之上形成第二牺牲材料层。 在一个实施例中，在第二牺牲层的顶表面上形成可渗透的防蚀层。 然后，实施例包括在第二牺牲材料层中形成互连线。 在一个实施例中，在形成互连线之后，第一和第二牺牲材料层通过可渗透的阻挡层去除。 根据一个实施例，然后可以用填充材料填充可渗透的防蚀层，以便硬化可渗透的防蚀层。

公开(公告)号：WO2016190887A1

公开(公告)日：2016-12-01

申请号：PCT/US2015/033060

申请日：2015-05-28

Applicant: INTEL CORPORATION

Inventor： KRYSAK, Marie ,  BRISTOL, Robert Lindsey ,  NYHUS, Paul Anton ,  LEESON, Michael J.

IPC: G03F7/004 ,  H01L21/027

CPC classification number: H01L21/76816 ,  G03F7/0045 ,  G03F7/0382 ,  G03F7/0392 ,  G03F7/095 ,  G03F7/2002 ,  G03F7/2004 ,  G03F7/2022 ,  G03F7/32 ,  G03F7/38 ,  H01L21/0271 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76808 ,  H01L21/76897 ,  H01L23/49827

Abstract: Embodiments of the invention include photoresist materials and methods of patterning photoresist materials. In an embodiment a photoresist material comprises a plurality of molecular glasses (MGs). In an embodiment, a glass transition temperature Tg of the photoresist material is less than an activation temperature needed to deblock blocking groups from the MGs. Embodiments include a method of patterning a photoresist material that comprises exposing the photoresist material with ultraviolet radiation. The method may also comprise, performing a first post exposure bake at a first temperature, that is less than the activation temperature needed to deblock blocking groups from the MGs, and performing a second post exposure bake at a second temperature that is approximately equal to or greater than the activation temperature needed to deblock blocking groups from the MGs.

Abstract translation: 本发明的实施例包括光刻胶材料和图案化光刻胶材料的方法。 在一个实施方案中，光致抗蚀剂材料包括多个分子眼镜（MG）。 在一个实施方案中，光致抗蚀剂材料的玻璃化转变温度Tg小于从MGs去除阻断基团所需的活化温度。 实施例包括图案化光致抗蚀剂材料的方法，其包括用紫外线辐射曝光光致抗蚀剂材料。 该方法还可以包括：在第一温度下进行第一后曝光烘烤，其小于从MG去除阻断基团所需的活化温度，以及在大约等于或等于的第二温度下进行第二后曝光烘烤 大于从MGs去除阻断组所需的活化温度。

公开(公告)号：WO2016153987A1

公开(公告)日：2016-09-29

申请号：PCT/US2016/023110

申请日：2016-03-18

Applicant: APPLIED MATERIALS, INC.

Inventor： FU, Xinyu ,  GANDIKOTA, Srinivas ,  CHANG, Mei ,  GANGULI, Seshadri ,  JIAN, Guoqiang ,  YANG, Yixiong ,  BANTHIA, Vikash ,  BAKKE, Jonathan

IPC: H01L21/205 ,  H01L21/3065

CPC classification number: H01L21/76816 ,  H01L21/32135 ,  H01L21/76843 ,  H01L21/76865 ,  H01L21/76877 ,  H01L21/76879

Abstract: Methods for etching a substrate are provided herein. In some embodiments, a method for etching a substrate disposed within a processing volume of a process chamber includes: (a) exposing a first layer disposed atop the substrate to a first gas comprising tungsten chloride (WClx) for a first period of time and at a first pressure, wherein x is 5 or 6; (b) purging the processing volume of the first gas using an inert gas for a second period of time; (c) exposing the substrate to a hydrogen-containing gas for a third period of time to etch the first layer after purging the processing volume of the first gas; and (d) purging the processing volume of the hydrogen-containing gas using the inert gas for a fourth period of time.

Abstract translation: 本发明提供蚀刻基板的方法。 在一些实施例中，用于蚀刻设置在处理室的处理体积内的衬底的方法包括：（a）将设置在衬底顶部的第一层暴露于包含氯化钨（WClx）的第一气体第一时间段 第一压力，其中x为5或6; （b）使用惰性气体吹扫第一气体的处理量第二段; （c）在清洗第一气体的处理容积之后，将衬底暴露于含氢气体持续第三时间以蚀刻第一层; 和（d）使用惰性气体净化含氢气体的处理量第四个时间段。