公开(公告)号：WO2011141726A3

公开(公告)日：2011-11-17

申请号：PCT/GB2011/050719

申请日：2011-04-12

Applicant: ARM LIMITED ,  SEAL, David James ,  CRASKE, Simon John

Inventor： SEAL, David James ,  CRASKE, Simon John

IPC: G06F9/30 ,  G06F9/32

Abstract: An instruction decoder (14) is responsive to a conditional compare instruction to generate control signals for controlling processing circuitry (4) to perform a conditional compare operation. The conditional compare operation comprises: (i) if a current condition state of the processing circuitry (4) passes a test condition, then performing a compare operation on a first operand and a second operand and setting the current condition state to a result condition state generated during the compare operation; and (ii) if the current condition state fails the test condition, then setting the current condition state to a fail condition state specified by the conditional compare instruction. The conditional compare instruction can be used to represent chained sequences of comparison operations where each individual comparison operation may test a different kind of relation between a pair of operands.

公开(公告)号：WO2011141726A2

公开(公告)日：2011-11-17

申请号：PCT/GB2011050719

申请日：2011-04-12

Applicant: ADVANCED RISC MACH LTD ,  SEAL DAVID JAMES ,  CRASKE SIMON JOHN

Inventor： SEAL DAVID JAMES ,  CRASKE SIMON JOHN

IPC: G06F9/30 ,  G06F9/32

CPC classification number: G06F9/30145 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/30167

Abstract: An instruction decoder (14) is responsive to a conditional compare instruction to generate control signals for controlling processing circuitry (4) to perform a conditional compare operation. The conditional compare operation comprises: (i) if a current condition state of the processing circuitry (4) passes a test condition, then performing a compare operation on a first operand and a second operand and setting the current condition state to a result condition state generated during the compare operation; and (ii) if the current condition state fails the test condition, then setting the current condition state to a fail condition state specified by the conditional compare instruction. The conditional compare instruction can be used to represent chained sequences of comparison operations where each individual comparison operation may test a different kind of relation between a pair of operands.

Abstract translation: 指令解码器（14）响应于条件比较指令以产生用于控制处理电路（4）执行条件比较操作的控制信号。 条件比较操作包括：（i）如果处理电路（4）的当前条件状态通过测试条件，则对第一操作数和第二操作数执行比较操作，并将当前条件状态设置为结果条件状态 在比较操作期间产生; 和（ii）如果当前条件状态未通过测试条件，则将当前状态设置为由条件比较指令指定的故障状态。 条件比较指令可以用于表示比较操作的链接序列，其中每个单独的比较操作可以测试一对操作数之间的不同种类的关系。

公开(公告)号：WO2012049475A1

公开(公告)日：2012-04-19

申请号：PCT/GB2011/051848

申请日：2011-09-29

Applicant: ARM LIMITED ,  CRASKE, Simon John

Inventor： CRASKE, Simon John

IPC: G06F9/30

CPC classification number: G06F9/30145

Abstract: A data processing apparatus, method and computer program are described that are capable of decoding instructions from different instruction sets. The method comprising: receiving an instruction; if an operation code of said instruction is an operation code of an instruction from a base set of instructions decoding said instruction according to decode rules for said base set of instructions; and if said operation code of said instruction is an operation code of an instruction from at least one further set of instructions decoding said instruction according to a set of decode rules determined by an indicator value indicating which of said at least one further set of instructions is currently to be decoded.

Abstract translation: 描述了能够解码来自不同指令集的指令的数据处理装置，方法和计算机程序。 该方法包括：接收指令; 如果所述指令的操作代码是根据用于所述基本指令集的解码规则的从指令解码的指令的基本指令的指令的操作代码; 并且如果所述指令的所述操作代码是来自根据由指示符值确定的一组解码规则解码所述指令的至少一个另外的指令的指令的操作代码，所述指示符值指示所述至少一个另外的一组指令是 目前要解码。

公开(公告)号：WO2010146328A1

公开(公告)日：2010-12-23

申请号：PCT/GB2010/000879

申请日：2010-04-30

Applicant: ARM LIMITED ,  CRASKE, Simon, John

Inventor： CRASKE, Simon, John

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/3013 ,  G06F9/461

Abstract: A data processing apparatus is described which comprises processing circuitry responsive to data processing instructions to execute integer data processing operations and floating point data processing operations, a first set of integer registers useable by the processing circuitry in executing the integer data processing operations, and a second set of floating point registers useable by the processing circuitry in executing the floating point data processing operations. The processing circuitry is responsive to an interrupt request to perform one of an integer state preservation function in which at least a subset of only the integer registers are copied to a stack memory, and a floating point state preservation function in which at least a subset of both the integer registers and the floating point registers are copied to the stack memory, the one of said integer state preservation function and the floating point state preservation function being selected by the processing circuitry in dependence on state information. In this way, it is possible to reduce the memory size requirement through reduced stack sizes, and to reduce the number of memory accesses required compared with the basic solution of always preserving floating point registers. As a result, power usage and interrupt latency can be reduced.

Abstract translation: 描述了一种数据处理装置，其包括响应于数据处理指令执行整数数据处理操作和浮点数据处理操作的处理电路，处理电路在执行整数数据处理操作时可使用的第一组整数寄存器，以及第二组 在执行浮点数据处理操作时由处理电路可使用的一组浮点寄存器。 所述处理电路响应中断请求执行整数状态保存功能之一，其中只有整数寄存器的至少一个子集被复制到堆栈存储器，以及浮点状态保存功能，其中至少一个子集 整数寄存器和浮点寄存器都被复制到堆栈存储器，所述整数状态保存功能和浮点状态保存功能之一由处理电路根据状态信息来选择。 以这种方式，可以通过减小堆栈大小来减少存储器大小的需求，并且与始终保留的浮点寄存器的基本解决方案相比，减少了所需的存储器访问数量。 因此，可以减少电力使用和中断延迟。

公开(公告)号：WO2012038710A1

公开(公告)日：2012-03-29

申请号：PCT/GB2011/051410

申请日：2011-07-25

Applicant: ARM LIMITED ,  WILLIAMS, Michael John ,  GRISENTHWAITE, Richard Roy ,  CRASKE, Simon John

Inventor： WILLIAMS, Michael John ,  GRISENTHWAITE, Richard Roy ,  CRASKE, Simon John

IPC: G06F11/36

CPC classification number: G06F11/3644 ,  G06F9/3004 ,  G06F9/30112 ,  G06F9/30149 ,  G06F9/30189 ,  G06F9/45554 ,  G06F11/3648

Abstract: A data processing apparatus is provided comprising data processing circuitry and debug circuitry. The debug circuitry controls operation of the processing circuitry when operating in a debug mode. The data processing circuitry determines upon entry into a debug mode a current operating state of the data processing apparatus. The data processing circuitry allocates one of a plurality of instruction sets to be used as a debug instruction set depending upon the determined current operating state.

Abstract translation: 提供了包括数据处理电路和调试电路的数据处理装置。 当在调试模式下操作时，调试电路控制处理电路的操作。 数据处理电路在进入调试模式时确定数据处理装置的当前操作状态。 数据处理电路根据确定的当前操作状态分配要用作调试指令集的多个指令集中的一个。

公开(公告)号：WO2012038708A1

公开(公告)日：2012-03-29

申请号：PCT/GB2011/050497

申请日：2011-03-14

Applicant: ARM LIMITED ,  CRASKE, Simon, John ,  SYMES, Dominic, Hugo ,  NYSTAD, Jørn

Inventor： CRASKE, Simon, John ,  SYMES, Dominic, Hugo ,  NYSTAD, Jørn

IPC: G06F7/552 ,  G06F7/483 ,  G06T15/00

CPC classification number: G06F17/10 ,  G06F5/012 ,  G06F7/483 ,  G06F7/5525 ,  G06F9/30036 ,  G06F2207/5521

Abstract: When performing vector normalisation upon floating point values, an approximate reciprocal value generating instruction is used to generate an approximate reciprocal value with a mantissa of one and an exponent given by a bitwise inversion of the exponent field of the input floating point number. A modified number of multiplication instruction is used which performs a multiplication giving the standard IEEE 754 results other than when a signed zero is multiplied by a signed infinity which results a signed predetermined substitute value, such as 2. The normalisation operation may be performed by calculating a scaling value in dependence upon the vector floating point value using the approximate reciprocal value generating instruction. Each of the input components may then be scaled using the modify multiplication instruction to generate a scaled vector floating point value formed of a plurality of scaled components. The magnitude of the scaled vector floating point value can then be calculated and each of the individual scaled components divided by this magnitude to generate a normalised vector floating point value. The scaling value may be set to 2, where C is an integer value selected such that the sum of the squares of the plurality of scale components is less than a predetermined limit value.

Abstract translation: 当在浮点值上执行向量归一化时，使用近似互逆值生成指令来生成一个尾数为1的近似互逆值，并且通过输入浮点数的指数字段的逐位反转给出的指数。 使用修正数量的乘法指令，其执行给出标准IEEE 754结果的乘法，而不是当有符号零乘以带符号的无穷大，其产生诸如2的已签名的预定替代值。归一化操作可以通过计算 根据使用近似互逆值生成指令的向量浮点值的缩放值。 然后可以使用修改乘法指令来对每个输入分量进行缩放，以生成由多个缩放分量形成的缩放向量浮点值。 然后可以计算缩放的向量浮点值的大小，并且每个单独的缩放的分量除以该大小以产生归一化的向量浮点值。 缩放值可以被设置为2，其中C是选择的整数值，使得多个刻度分量的平方和小于预定极限值。

公开(公告)号：WO2012095619A1

公开(公告)日：2012-07-19

申请号：PCT/GB2011/052353

申请日：2011-11-29

Applicant: ARM LIMITED ,  HORLEY, John ,  CRASKE, Simon ,  GIBBS, Michael ,  GILKERSON, Paul

Inventor： HORLEY, John ,  CRASKE, Simon ,  GIBBS, Michael ,  GILKERSON, Paul

IPC: G06F9/38 ,  G06F11/34 ,  G06F11/36

CPC classification number: G06F11/3495 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/30145 ,  G06F11/348

Abstract: A processing circuit (4) is responsive to at least one conditional instruction to perform a conditional operation in dependence on a current value of a subset of at least one condition flag (22). A trace circuit (6) is provided for generating trace data elements indicative of operations performed by the processing circuit (4). When the processing circuit (4) processes at least one selected instruction, then the trace circuit (6) generates a trace data element including a traced condition value indicating at least the subset of condition flags (22) required to determine the outcome of the conditional instruction. A corresponding diagnostic apparatus (12) uses the traced condition value to determine a processing outcome of the at least one conditional instruction.

Abstract translation: 处理电路（4）响应于至少一个条件指令，以根据至少一个条件标志（22）的子集的当前值执行条件操作。 提供跟踪电路（6），用于产生指示由处理电路（4）执行的操作的跟踪数据元素。 当处理电路（4）处理至少一个所选择的指令时，跟踪电路（6）产生跟踪数据元素，跟踪数据元素包括跟踪条件值，该跟踪条件值至少指示条件标志子集（22），以确定条件结果 指令。 相应的诊断装置（12）使用跟踪条件值来确定至少一个条件指令的处理结果。

公开(公告)号：WO2012056207A1

公开(公告)日：2012-05-03

申请号：PCT/GB2011/051820

申请日：2011-09-27

Applicant: ARM LIMITED ,  CRASKE, Simon, John ,  TEYSSIER, Melanie Emanuelle Lucie ,  HUOT, Nicolas Jean Phillippe ,  GRANDOU, Gilles Eric

Inventor： CRASKE, Simon, John ,  TEYSSIER, Melanie Emanuelle Lucie ,  HUOT, Nicolas Jean Phillippe ,  GRANDOU, Gilles Eric

IPC: G06F12/14

CPC classification number: G06F12/1416 ,  G06F12/0802 ,  G06F12/1441 ,  G06F12/145 ,  G06F12/1458 ,  Y02D10/13

Abstract: A data processing system (2) includes memory protection circuitry (10) storing access control data for controlling accesses to data at memory addresses within a main memory (16). An access control cache (14) may, in one embodiment, store access control data when the access control data is indicated by the memory protection circuitry (10) to be cachable. In another embodiment access control data is stored within the access control cache with determined address range data for reach determination of access control data by the memory protection circuitry. If the access control cache (14) is storing access control data for a memory access request, then the access control data stored within the access control cache (14) is used in place of access control data retrieved form the memory protection circuitry (10). In the first embodiment, access control data may be determined to be cachable is if is associated with a region of memory addresses within a plurality of hierarchically ordered memory addresses that is a highest order region which encompasses all the memory addresses within that region.

Abstract translation: 数据处理系统（2）包括存储器保护电路（10），存储用于控制对主存储器（16）内的存储器地址的数据的访问的访问控制数据。 在一个实施例中，当访问控制数据由存储器保护电路（10）指示为可高速缓存时，访问控制高速缓存（14）可以存储访问控制数据。 在另一个实施例中，访问控制数据被存储在具有确定的地址范围数据的访问控制高速缓存内，以由存储器保护电路进行访问控制数据的确定。 如果访问控制缓存（14）正在存储用于存储器访问请求的访问控制数据，则使用存储在访问控制高速缓存（14）内的访问控制数据来代替从存储器保护电路（10）检索的访问控制数据， 。 在第一实施例中，如果与包含该区域内的所有存储器地址的最高级存储器地址的多个层次顺序的存储器地址中的存储器地址的区域相关联，则可以确定访问控制数据可高速缓存。

公开(公告)号：WO2012049474A1

公开(公告)日：2012-04-19

申请号：PCT/GB2011/051847

申请日：2011-09-29

Applicant: ARM LIMITED ,  CRASKE, Simon John ,  GRISENTHWAITE, Richard Roy ,  STEPHENS, Nigel John

Inventor： CRASKE, Simon John ,  GRISENTHWAITE, Richard Roy ,  STEPHENS, Nigel John

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30003 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/3842

Abstract: A data processing apparatus, method and computer program that perform an operation on one data element such as a register and then conditionally select either that register or a further register on which no operation has been performed. The apparatus comprises an instruction decoder configured to decode at least one conditional select instruction, said at least one conditional select instruction specifying a primary source register, a secondary source register, a destination register, a condition, and an operation to be performed on a data element from the secondary source register; a data processor configured to perform data processing operations controlled by the instruction decoder wherein: the data processor is responsive to the decoded at least one conditional select instruction and the condition having a predetermined outcome to perform the operation on the data element from the secondary source register to form a resultant data element and to store the resultant data element in the destination register; and the data processor is responsive to the decoded at least one conditional select instruction and the condition not having the predetermined outcome to form the resultant data element from the data element from the primary register and to store the resultant data element in the destination register.

Abstract translation: 一种数据处理装置，方法和计算机程序，其对诸如寄存器的一个数据元素执行操作，然后有条件地选择该寄存器或其上没有进行任何操作的另外的寄存器。 该装置包括指令解码器，其被配置为对至少一个条件选择指令进行解码，所述至少一个条件选择指令指定主源寄存器，次源寄存器，目的地寄存器，条件以及对数据执行的操作 来自次级源寄存器的元件; 配置为执行由指令解码器控制的数据处理操作的数据处理器，其中：数据处理器响应于解码的至少一个条件选择指令和具有预定结果的条件，以从次级源寄存器对数据元素执行操作 以形成结果数据元素并将结果数据元素存储在目的寄存器中; 并且数据处理器响应于解码的至少一个条件选择指令和不具有预定结果的条件，以从主寄存器的数据元素形成结果数据元素，并将结果数据元素存储在目的寄存器中。