公开(公告)号：WO2012069798A1

公开(公告)日：2012-05-31

申请号：PCT/GB2011/051841

申请日：2011-09-29

Applicant: ARM LIMITED ,  SEAL, David James ,  GRISENTHWAITE, Richard Roy ,  STEPHENS, Nigel John

Inventor： SEAL, David James ,  GRISENTHWAITE, Richard Roy ,  STEPHENS, Nigel John

IPC: G06F9/30 ,  G06F7/76

CPC classification number: G06F9/3016 ,  G06F7/764 ,  G06F7/768 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3887

Abstract: A data processing apparatus (2) comprises a processing circuit (4) and instruction decoder (6). A bitfield manipulation instruction controls the processing apparatus (2) to generate at least one result data element from corresponding first and second source data elements src1, src2. Each result data element includes a portion corresponding to a bitfield bf of the corresponding first source data element src1. Bits of the result data element that are more significant than the inserted bitfield bf have a prefix value p that is selected, based on a control value specified by the instruction, as one of a first prefix value having a zero value, a second prefix value having the value of a portion of the corresponding second source data element src2, and a third prefix value corresponding to a sign extension of the bitfield bf of the first source data element src1.

Abstract translation: 数据处理装置（2）包括处理电路（4）和指令解码器（6）。 位字段操作指令控制处理装置（2）从相应的第一和第二源数据元素src1，src2生成至少一个结果数据元素。 每个结果数据元素包括对应于相应的第一源数据元素src1的位字段bf的部分。 比插入的位字段bf更重要的结果数据元素的位具有基于由指令指定的控制值被选择的前缀值p作为具有零值的第一前缀值，第二前缀值 具有相应的第二源数据元素src2的一部分的值，以及与第一源数据元素src1的位域bf的符号扩展对应的第三前缀值。

公开(公告)号：WO2011114121A1

公开(公告)日：2011-09-22

申请号：PCT/GB2011/050306

申请日：2011-02-16

Applicant: ARM LIMITED ,  GRISENTHWAITE, Richard, Roy ,  SEAL, David, James

Inventor： GRISENTHWAITE, Richard, Roy ,  SEAL, David, James

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38

CPC classification number: G06F9/30112 ,  G06F9/30123 ,  G06F9/30138 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/384 ,  G06F9/3863

Abstract: A processor (4) is provided which supports a first instruction set specifying 32-bit architectural registers and a second instruction set specifying 64-bit architectural registers. Each of these instruction sets is presented with its own set of architectural registers for use. The first set of registers presented to the first instruction set has a one-to-one mapping to the second set of registers presented to this second instruction set. The registers which are provided in hardware are 64-bit registers. In some embodiments, when executing program instructions of the first instruction set, only the least significant portion of these 64-bit registers are accessed and manipulated with the remaining most significant portion of the registers being left unaltered. Register specifying fields within instructions of the first instruction set are decoded together with a current exception mode to determine which architectural register to use whereas the second instruction set uses register specifying fields without a dependence upon exception mode to determine which architectural register are to be used.

Abstract translation: 提供了一种处理器（4），其支持指定32位架构寄存器的第一指令集和指定64位架构寄存器的第二指令集。 这些指令集中的每一个都带有自己的一组架构寄存器供使用。 呈现给第一指令集的第一组寄存器具有与呈现给该第二指令集的第二组寄存器的一对一映射。 在硬件中提供的寄存器是64位寄存器。 在一些实施例中，当执行第一指令集的程序指令时，只有这些64位寄存器的最低有效部分被访问和操作，其中最重要的寄存器部分保持不变。 在第一指令集的指令内的寄存器指定字段与当前异常模式一起被解码以确定要使用的架构寄存器，而第二指令集使用寄存器指定字段而不依赖于异常模式来确定要使用哪个架构寄存器。

公开(公告)号：WO2011114125A1

公开(公告)日：2011-09-22

申请号：PCT/GB2011/050397

申请日：2011-03-01

Applicant: ARM LIMITED ,  GRISENTHWAITE, Richard, Roy ,  SEAL, David, James ,  RAPHALEN, Philippe, Jean-Pierre ,  SMITH, Lee, Douglas

Inventor： GRISENTHWAITE, Richard, Roy ,  SEAL, David, James ,  RAPHALEN, Philippe, Jean-Pierre ,  SMITH, Lee, Douglas

IPC: G06F9/30 ,  G06F9/312 ,  G06F1/32 ,  G06F21/00

CPC classification number: G06F9/3016 ,  G06F9/3001 ,  G06F9/30112 ,  G06F9/3861 ,  G06F21/577 ,  G06F21/70 ,  G06F2221/2145

Abstract: A data processing system (2) is provided with processing circuitry (8,10,12) as well as a bank of 64-bit registers (6). An instruction decoder (14) decodes arithmetic instructions and logical instruction specifying arithmetic operations and logical operations to be performed upon operands stored within the 64-bit registers (6). The instruction decoder (14) is responsive to an operand size field SF within the arithmetic instructions and the logical instructions specifying whether the operands are 64-bit operands or 32-bit operands. Each 64-bit register stores either a single 64-bit operand or a single 32-bit operand. For a given arithmetic instruction and logical instruction either all of the operands are 64-bit operands or all of the operands are 32-bit operands. A plurality of exception levels arranged in a hierarchy of exception levels may be supported. If a switch is made to a lower exception level, then a check is made as to whether or not a register being used was previously subject to a 64-bit write to that register. If such a 64-bit write had previously taken place to that register, then the upper 32-bits are flushed so as to avoid data leakage from the higher exception level.

Abstract translation: 数据处理系统（2）具有处理电路（8,10,12）以及一组64位寄存器（6）。 指令解码器（14）对存储在64位寄存器（6）中的操作数执行的运算指令和指定算术运算和逻辑运算的逻辑指令进行解码。 指令解码器（14）响应于算术指令内的操作数大小字段SF，以及指定操作数是64位操作数还是32位操作数的逻辑指令。 每个64位寄存器存储单个64位操作数或单个32位操作数。 对于给定的算术指令和逻辑指令，所有操作数都是64位操作数，或者所有操作数都是32位操作数。 可以支持以异常级别分层布置的多个异常级别。 如果将交换机设置为较低的异常级别，则检查所使用的寄存器是否先前对该寄存器进行64位写操作。 如果先前对该寄存器进行了这样的64位写操作，则高位32位被刷新，以避免数据从较高异常级别泄漏。

公开(公告)号：WO2007048988A1

公开(公告)日：2007-05-03

申请号：PCT/GB2005/004131

申请日：2005-10-26

Applicant: ARM LIMITED ,  SEAL, David, James

Inventor： SEAL, David, James

IPC: G06F9/38 ,  G06F9/42 ,  G06F9/30 ,  G06F9/46

CPC classification number: G06F9/30101 ,  G06F9/322 ,  G06F9/3804 ,  G06F9/381

Abstract: A data processing apparatus and method are provided for handling procedure call instructions. The data processing apparatus has processing logic for performing data processing operations specified by program instructions fetched from a sequence of addresses, at least one of the program instructions being a procedure call instruction specifying a branch operation to be performed. Further, a control value is stored within control storage, and the processing logic is operable in response to a control value modifying instruction to modify that control value. If the control value is clear, the processing logic is operable in response to the procedure call instruction to generate a return address value in addition to performing the branch operation, whereas if the control value is set, the processing logic is operable in response to the procedure call instruction to suppress generation of the return address value and to cause the control value to be clear in addition to performing the branch operation. This provides significant flexibility in how procedure call instructions are used within the data processing apparatus.

Abstract translation: 提供了一种用于处理过程调用指令的数据处理装置和方法。 数据处理装置具有用于执行由地址序列取出的程序指令指定的数据处理操作的处理逻辑，程序指令中的至少一个是指定要执行的分支操作的过程调用指令。 此外，控制值存储在控制存储器中，并且处理逻辑可响应于控制值修改指令而操作以修改该控制值。 如果控制值清楚，则除了执行分支操作之外，响应于过程调用指令也可以处理逻辑以产生返回地址值，而如果设置了控制值，则处理逻辑可响应于 过程调用指令，以抑制返回地址值的生成，并且除了执行分支操作之外还使控制值清除。 这在数据处理设备中如何使用过程调用指令提供了显着的灵活性。

公开(公告)号：WO2012120267A1

公开(公告)日：2012-09-13

申请号：PCT/GB2012/050158

申请日：2012-01-26

Applicant: ARM LIMITED ,  STEPHENS, Nigel John ,  SEAL, David James

Inventor： STEPHENS, Nigel John ,  SEAL, David James

IPC: G06F9/34 ,  G06F9/30 ,  G06F9/32 ,  G06F9/355

CPC classification number: G06F9/3557 ,  G06F9/30007 ,  G06F9/30112 ,  G06F9/30167 ,  G06F9/342 ,  G06F9/345 ,  G06F2212/657

Abstract: A data processing apparatus is provided comprising processing circuitry and an instruction decoder responsive to program instructions to control processing circuitry to perform the data processing. The instruction decoder is responsive to an address calculating instruction to perform an address calculating operation for calculating a partial address result from a non-fixed reference address and a partial offset value such that a full address specifying a memory location of an information entity is calculable from said partial address result using at least one supplementary program instruction. The partial offset value has a bit-width greater than or equal to said instruction size and is encoded within at least one partial offset field of said address calculating instruction. A corresponding data processing method, virtual machine and computer program product are also provided.

Abstract translation: 提供了一种数据处理装置，其包括响应于程序指令的处理电路和指令解码器，以控制处理电路执行数据处理。 指令解码器响应于地址计算指令来执行地址计算操作，用于从非固定参考地址和部分偏移值计算部分地址结果，使得可以从...计算指定信息实体的存储位置的完整地址 所述部分地址结果使用至少一个补充程序指令。 部分偏移值具有大于或等于所述指令大小的位宽，并且被编码在所述地址计算指令的至少一个部分偏移字段内。 还提供了相应的数据处理方法，虚拟机和计算机程序产品。

公开(公告)号：WO2011141726A3

公开(公告)日：2011-11-17

申请号：PCT/GB2011/050719

申请日：2011-04-12

Applicant: ARM LIMITED ,  SEAL, David James ,  CRASKE, Simon John

Inventor： SEAL, David James ,  CRASKE, Simon John

IPC: G06F9/30 ,  G06F9/32

Abstract: An instruction decoder (14) is responsive to a conditional compare instruction to generate control signals for controlling processing circuitry (4) to perform a conditional compare operation. The conditional compare operation comprises: (i) if a current condition state of the processing circuitry (4) passes a test condition, then performing a compare operation on a first operand and a second operand and setting the current condition state to a result condition state generated during the compare operation; and (ii) if the current condition state fails the test condition, then setting the current condition state to a fail condition state specified by the conditional compare instruction. The conditional compare instruction can be used to represent chained sequences of comparison operations where each individual comparison operation may test a different kind of relation between a pair of operands.

公开(公告)号：WO2011141726A2

公开(公告)日：2011-11-17

申请号：PCT/GB2011050719

申请日：2011-04-12

Applicant: ADVANCED RISC MACH LTD ,  SEAL DAVID JAMES ,  CRASKE SIMON JOHN

Inventor： SEAL DAVID JAMES ,  CRASKE SIMON JOHN

IPC: G06F9/30 ,  G06F9/32

CPC classification number: G06F9/30145 ,  G06F9/30021 ,  G06F9/30072 ,  G06F9/30167

Abstract: An instruction decoder (14) is responsive to a conditional compare instruction to generate control signals for controlling processing circuitry (4) to perform a conditional compare operation. The conditional compare operation comprises: (i) if a current condition state of the processing circuitry (4) passes a test condition, then performing a compare operation on a first operand and a second operand and setting the current condition state to a result condition state generated during the compare operation; and (ii) if the current condition state fails the test condition, then setting the current condition state to a fail condition state specified by the conditional compare instruction. The conditional compare instruction can be used to represent chained sequences of comparison operations where each individual comparison operation may test a different kind of relation between a pair of operands.

Abstract translation: 指令解码器（14）响应于条件比较指令以产生用于控制处理电路（4）执行条件比较操作的控制信号。 条件比较操作包括：（i）如果处理电路（4）的当前条件状态通过测试条件，则对第一操作数和第二操作数执行比较操作，并将当前条件状态设置为结果条件状态 在比较操作期间产生; 和（ii）如果当前条件状态未通过测试条件，则将当前状态设置为由条件比较指令指定的故障状态。 条件比较指令可以用于表示比较操作的链接序列，其中每个单独的比较操作可以测试一对操作数之间的不同种类的关系。