公开(公告)号：WO1996010841A1

公开(公告)日：1996-04-11

申请号：PCT/US1995013078

申请日：1995-09-28

Applicant: VLSI TECHNOLOGY, INC. ,  EISENSTADT, Robert, E. ,  ROHRS, Kurt, D.

Inventor： VLSI TECHNOLOGY, INC.

IPC: H01L23/495

CPC classification number: H01L23/49805 ,  H01L23/49572 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/15173

Abstract: A semiconductor die (18) includes a multiplicity of die bonding pads (20) arrayed about the periphery of a surface of the die (18), and has a plurality of global signal bonding pad (21) located centrally to the peripheral die bonding pads (20). Global signals are those signals which are routed extensively throughout the semiconductor die (18), and include, for example, the power signal, ground signal, and clock signal. When a global signal is provided to the center of the semiconductor chip (18), the signal can be transmitted across the chip with a minimum of skew. In addition, the size of the electrically conductive traces which transmit the global signal within the chip can be decreased, allowing reductions in both semiconductor chip size, and cost. In some embodiments, the global signal inputs are provided in an interconnected lead net (17G) at or near the center of the die surface.

Abstract translation: 半导体管芯（18）包括围绕管芯（18）的表面的周边排列的多个管芯接合焊盘（20），并且具有多个位于外围管芯接合焊盘中心的全局信号焊盘（21） （20）。 全局信号是在整个半导体管芯（18）中广泛布线的那些信号，并且包括例如功率信号，接地信号和时钟信号。 当全局信号被提供给半导体芯片（18）的中心时，信号可以以最小的偏斜跨越芯片传输。 此外，可以减小在芯片内传输全局信号的​​导电迹线的尺寸，从而允许半导体芯片尺寸和成本的降低。 在一些实施例中，全局信号输入在模具表面的中心处或附近设置在互连的引线网（17G）中。