公开(公告)号：WO1996037044A1

公开(公告)日：1996-11-21

申请号：PCT/US1996007098

申请日：1996-05-16

Applicant: VLSI TECHNOLOGY, INC. ,  BHUSHAN, Bharat ,  ARCUS, Christopher, A. ,  TA, Paul, D.

Inventor： VLSI TECHNOLOGY, INC.

IPC: H03K03/0231

CPC classification number: H03L7/0995 ,  H03K3/0231 ,  H03K3/0322

Abstract: A ring-style, multi-stage VCO of a phase lock loop circuit (100) includes two or more differential amplifier stages. The phase lock loop (100) includes a lowpass filter (108) connected between a control voltage terminal and a voltage-to-current converter stage (110), which includes a first source-follower MOS transistor M1 with a source resistor R1 and a second diode-connected MOS transistor M2 connected to its drain terminal. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN_ terminal. The drain terminal of MOS transistor M4 provides an OUT_ signal for the differential amplifier stage and the drain terminal of MOS transistor M5 provides an OUT signal for the differential amplifier stage. A MOS transistor M6 forms a load impedance for MOS transistor M4 and a MOS transistor M7 forms a load impedance for MOS transistor M5. The gate terminals of M6 and M7 are connected to the voltage control input terminal of the phase lock loop.

Abstract translation: 锁相环电路（100）的环形多级VCO包括两个或更多个差分放大器级。 锁相环（100）包括连接在控制电压端子和电压 - 电流转换器级（110）之间的低通滤波器（108），该低通滤波器包括具有源电阻器R1的第一源极跟随器MOS晶体管M1和 连接到其漏极端子的第二二极管连接的MOS晶体管M2。 差分放大器级包括电流源MOS晶体管M10，其电流源MOS晶体管M10具有连接到第一MOS晶体管M1的漏极的栅极端，以电流镜像M1的漏极电流。 差分放大器级还包括连接到电流源MOS晶体管M10的漏极端子的一对MOS晶体管M4和M5。 MOS晶体管M4的栅极端子是IN端子，MOS晶体管M5的栅极端子是IN_端子。 MOS晶体管M4的漏极端子为差分放大器级提供OUT_信号，MOS晶体管M5的漏极端为差分放大器级提供OUT信号。 MOS晶体管M6形成MOS晶体管M4的负载阻抗，MOS晶体管M7形成MOS晶体管M5的负载阻抗。 M6和M7的门极连接到锁相环的电压控制输入端。

公开(公告)号：WO1996018945A1

公开(公告)日：1996-06-20

申请号：PCT/US1995016302

申请日：1995-12-14

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  DOCKSER, Kenneth, A.

IPC: G06F09/38

CPC classification number: G06F9/3808 ,  G06F9/3802 ,  G06F9/3806

Abstract: A Harvard architecture data processing system includes a processor, main memory, an instruction cache, and a data cache. As is generally known with the Harvard architecture, these components are interconnected by an instruction bus, an instruction address bus, a data bus, and a data address bus. The instruction bus includes a branch target section and a general instruction section. For each instruction request by the processor, both sections are examined to determine if the requested instruction is in the cache. If it is, it is transmitted from the cache to the processor. If it is not, an instruction line including the requested instruction is fetched from main memory. If the requested instruction represents a jump (the result of an unconditional branch or a conditional branch the condition of which is met) the fetched instruction line can be stored only in the branch target section. If the requested instruction is simply the one located at the address one above that of the previous instruction, the fetched instruction line can only be stored in the general instruction section. This approach preserves branch targets in cache, while allowing all cached instructions to be available to the processor irrespective of whether a jump is called for.

Abstract translation: 哈佛架构数据处理系统包括处理器，主存储器，指令高速缓存和数据高速缓存。 如哈佛结构通常所知，这些组件通过指令总线，指令地址总线，数据总线和数据地址总线相互连接。 指令总线包括分支目标部分和通用指令部分。 对于处理器的每个指令请求，检查两个部分以确定所请求的指令是否在高速缓存中。 如果是，则从缓存发送到处理器。 如果不是，则从主存储器取出包含请求指令的指令行。 如果所请求的指令表示跳转（无条件分支的结果或满足条件分支的条件分支），则所获取的指令行只能存储在分支目标部分中。 如果所请求的指令仅仅是位于比上一个指令的地址高一个地址的指令，则所获取的指令行只能存储在通用指令部分中。 该方法保留缓存中的分支目标，同时允许所有高速缓存的指令对于处理器可用，而不管是否要求跳转。

公开(公告)号：WO1996012298A1

公开(公告)日：1996-04-25

申请号：PCT/US1994011812

申请日：1994-10-17

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  MASSINGILL, Thomas, J.

IPC: H01L23/31

CPC classification number: H01L23/49816 ,  H01L23/13 ,  H01L23/142 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: A high performance ball grid array is disclosed in which a ball grid array is modified to include a body having a recessed central cavity. The inclusion of a central cavity allows the die to be mounted on the same side of the package in which the solder balls are located. Since the die is mounted on the same side as that of the solder balls, only one set of leads is needed to electrically connect the die to the solder balls, thus requiring only one layer of electrically conductive material within the package, as opposed to conventional ball grid array packages which required two metal layers. In addition, since only one metal layer is needed, the present invention is able to operate without the use of electrically conductive vias. The die is connected via wirebonds to bonding areas located on the package. Each of the bonding areas is substantially co-planar, and each bonding area is located at a different distance from one edge of the central cavity, thereby forming a staggered arrangement. The advantage of positioning the bonding areas in a staggered arrangement is that it enables the spacing between each of the adjacent bonding wires to be maintained, thereby avoiding fan-out of the bonding wires and avoiding the need for multi-level bonding areas in the package.

Abstract translation: 公开了一种高性能球栅阵列，其中球栅阵列被修改为包括具有凹陷中心腔的主体。 包括中心腔允许模具安装在焊球所在的封装的同一侧。 由于芯片安装在与焊球相同的一侧，所以只需要一组引线将裸片与焊球电连接，因此与封装中只需要一层导电材料，这与传统的 需要两个金属层的球栅阵列封装。 此外，由于仅需要一个金属层，所以本发明能够在不使用导电通孔的情况下工作。 管芯通过引线连接到位于封装上的接合区域。 每个结合区域基本上是共面的，并且每个结合区域位于与中心空腔的一个边缘不同的距离处，从而形成交错排列。 以交错布置的方式定位接合区域的优点是能够保持每个相邻的接合线之间的间隔，从而避免了接合线的扇出，并且避免了对封装中的多层结合区域的需要 。

公开(公告)号：WO1996010841A1

公开(公告)日：1996-04-11

申请号：PCT/US1995013078

申请日：1995-09-28

Applicant: VLSI TECHNOLOGY, INC. ,  EISENSTADT, Robert, E. ,  ROHRS, Kurt, D.

Inventor： VLSI TECHNOLOGY, INC.

IPC: H01L23/495

CPC classification number: H01L23/49805 ,  H01L23/49572 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/16245 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01079 ,  H01L2924/15173

Abstract: A semiconductor die (18) includes a multiplicity of die bonding pads (20) arrayed about the periphery of a surface of the die (18), and has a plurality of global signal bonding pad (21) located centrally to the peripheral die bonding pads (20). Global signals are those signals which are routed extensively throughout the semiconductor die (18), and include, for example, the power signal, ground signal, and clock signal. When a global signal is provided to the center of the semiconductor chip (18), the signal can be transmitted across the chip with a minimum of skew. In addition, the size of the electrically conductive traces which transmit the global signal within the chip can be decreased, allowing reductions in both semiconductor chip size, and cost. In some embodiments, the global signal inputs are provided in an interconnected lead net (17G) at or near the center of the die surface.

Abstract translation: 半导体管芯（18）包括围绕管芯（18）的表面的周边排列的多个管芯接合焊盘（20），并且具有多个位于外围管芯接合焊盘中心的全局信号焊盘（21） （20）。 全局信号是在整个半导体管芯（18）中广泛布线的那些信号，并且包括例如功率信号，接地信号和时钟信号。 当全局信号被提供给半导体芯片（18）的中心时，信号可以以最小的偏斜跨越芯片传输。 此外，可以减小在芯片内传输全局信号的​​导电迹线的尺寸，从而允许半导体芯片尺寸和成本的降低。 在一些实施例中，全局信号输入在模具表面的中心处或附近设置在互连的引线网（17G）中。

公开(公告)号：WO1996001009A1

公开(公告)日：1996-01-11

申请号：PCT/US1995007130

申请日：1995-06-05

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  OH, Sung-Hun ,  TAYLOR, Richard, M.

IPC: H03K17/16

CPC classification number: H03K19/018585 ,  H03K19/00361

Abstract: A programmable output pad (66) is disclosed that reduces ground bounce noise and power supply noise under different power supply values and under different load conditions. The programmable output pad (66) comprises a pre-driver, a driver, and a controllable delay. The pre-driver transfers a signal from the output pad (66) to the driver which, in turn, transfers the signal from the pre-driver to an output of the output pad (66). The controllable delay provides one or more resistors, transistors, transmission gates (90, 92) or equivalents thereof at the input of the driver which are controlled in order to provide a plurality of different time delays. By selecting these different time delays, the activation of the driver is delayed by different amounts of time. For a given power supply value and load condition, selection of the proper delay effectively reduces both the ground bounce noice on the ground supply of the programmable output pad (66) and the noise on the power supply of the programmable output pad (66).

Abstract translation: 公开了一种可编程输出焊盘（66），其在不同的电源值和不同的负载条件下降低了接地反弹噪声和电源噪声。 可编程输出焊盘（66）包括预驱动器，驱动器和可控延迟。 预驱动器将信号从输出焊盘（66）传送到驱动器，驱动器又将信号从预驱动器传送到输出焊盘（66）的输出端。 可控延迟在驱动器的输入处提供一个或多个电阻器，晶体管，传输门（90,92）或其等同物，其被控制以提供多个不同的时间延迟。 通过选择这些不同的时间延迟，驱动器的激活被延迟不同的时间量。 对于给定的电源值和负载条件，适当延迟的选择有效地减少了可编程输出焊盘（66）的接地电源上的接地反弹噪声和可编程输出焊盘（66）的电源上的噪声。

公开(公告)号：WO1995021457A1

公开(公告)日：1995-08-10

申请号：PCT/US1995001155

申请日：1995-01-26

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  BRUGGE, Hunter, Barham

IPC: H01J37/34

CPC classification number: H01J37/3447 ,  H01J37/3408

Abstract: A sputter deposition system (10) includes a mobile collimator (20). The collimator can be magnetically moved into and out of a position between a wafer (28) and a target of material (26) to be sputtered onto the wafer. In addition, magnets (36, 38) are used to levitate the collimator so that it can be removed without solid-solid friction and the contamination it can cause. The magnets used for levitation are part of a control loop that maintains the orientation of the collimator parallel to the wafer. The system alllows for a combination of good deposition step coverage and high fabrication throughput while minimizing opportunities for contamination and breakage that can occur when the wafer is transferred between chambers (12).

Abstract translation: 溅射沉积系统（10）包括移动准直器（20）。 准直器可以被磁性地移入和移出晶片（28）和材料（26）的靶之间，以溅射到晶片上。 此外，磁体（36,38）用于悬浮准直器，使得其可以被移除而没有固体 - 摩擦和它可能引起的污染。 用于悬浮的磁体是保持准直器平行于晶片的取向的控制回路的一部分。 该系统适用于良好的沉积步骤覆盖和高制造生产量的组合，同时最小化当晶片在室（12）之间转移时可能发生的污染和断裂的机会。

公开(公告)号：WO1995012215A1

公开(公告)日：1995-05-04

申请号：PCT/US1994011175

申请日：1994-10-03

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  NOWAK, Edward, D.

IPC: H01L27/11

CPC classification number: H01L28/20 ,  H01L21/743 ,  H01L27/11 ,  H01L27/1112 ,  H01L27/1203 ,  Y10S257/903

Abstract: A resistor is connected to the source/drain of a transistor and used as a load element of a memory cell. A trench (19) is formed which extends from a top of the wafer through an isolation region (11) of the wafer to a silicon base (10) of the wafer. The silicon base (10) of the wafer is located below the isolation region (11) of the wafer. A resistive layer of material (22) is formed in the trench (19). The resistive layer extends from the top of the wafer through the isolation region (11) of the wafer and is electrically connected to the silicon base (10) of the wafer. The resistor is connected to other circuitry on the wafer, for example, by implanting into the wafer atoms of a first conductivity type into a region immediately adjacent to the resistive layer of material (22) in the trench (19). In the preferred embodiment, the resistive layer of material (22) is deposited polysilicon.

Abstract translation: 电阻器连接到晶体管的源极/漏极，并用作存储器单元的负载元件。 形成了从晶片的顶部通过晶片的隔离区域（11）延伸到晶片的硅基底（10）的沟槽（19）。 晶片的硅基（10）位于晶片的隔离区（11）的下方。 材料（22）的电阻层形成在沟槽（19）中。 电阻层从晶片的顶部延伸通过晶片的隔离区域（11）并且电连接到晶片的硅基底（10）。 电阻器连接到晶片上的其它电路，例如通过将第一导电类型的晶片原子注入到与沟槽（19）中的材料（22）的电阻层紧邻的区域中。 在优选实施例中，材料（22）的电阻层被沉积多晶硅。

公开(公告)号：WO1995008839A1

公开(公告)日：1995-03-30

申请号：PCT/US1994010708

申请日：1994-09-22

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  BRUGGE, Hunter, B.

IPC: H01L21/285

CPC classification number: H01L21/28518 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S438/952 ,  H01L2924/00

Abstract: A first metallic layer (16) is deposited over the substrate (10) and the contact well (14) formed therein. The first metallic layer (16) is then exposed to a gas to allow the gas to stuff the first metallic layer, thereby improving the barrier characteristics of the first metallic layer. A second metallic layer (22) is deposited over the first stuffed metallic layer (16). A third metallic layer (24) is then deposited over the second metallic layer. An anti-reflective fourth layer of metal (26) is then deposited over the third metallic layer (24). The exposure of the first metallic layer (16) to a gas and all of the metal layer deposition steps are performed in a low-pressure environment. Also, as an result of subsequent processing steps required in the formation of semiconductor devices, the portions of the first metallic layer which are present outside of the contact well are removed. The remaining portion of the first metallic layer forms a self-aligned silicide within the contact well.

Abstract translation: 第一金属层（16）沉积在衬底（10）和形成在其中的接触阱（14）之上。 然后将第一金属层（16）暴露于气体以允许气体填充第一金属层，从而改善第一金属层的阻挡特性。 第二金属层（22）沉积在第一填充金属层（16）上。 然后在第二金属层上沉积第三金属层（24）。 然后在第三金属层（24）上沉积抗反射第四层金属（26）。 第一金属层（16）暴露于气体和所有金属层沉积步骤都是在低压环境下进行的。 此外，作为形成半导体器件所需的后续处理步骤的结果，除去存在于接触阱外部的第一金属层的部分。 第一金属层的剩余部分在接触阱内形成自对准的硅化物。

公开(公告)号：WO1995000973A1

公开(公告)日：1995-01-05

申请号：PCT/US1994006739

申请日：1994-06-13

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  GROOVER, Richard ,  SHU, William ,  LEE, Sang, S. ,  FUJIMOTO, George

IPC: H01L23/495

CPC classification number: H01L23/16 ,  H01L23/057 ,  H01L23/4334 ,  H01L23/49531 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/4911 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15312 ,  H01L2924/16195 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: An integrated-circuit package assembly includes a separate silicon substrate (34) to which an integrated-circuit die (32) is fixed. The separate silicon substrate (34) serves as a heat spreader for the integrated-circuit die (32). The separate silicon substrate (34) to which the integrated-circuit die (32) is fixed is packaged in either a molded package body (80) or a cavity-type package body (120). For the molded package body (80), the package body is molded around a leadframe (42), the integrated-circuit die (32), and the separate silicon substrate (34) to which the integrated-circuit die (32) is fixed. For a molded package body (80), the leadframe (42) has bonding fingers formed at the inward ends thereof which are attached to the separate silicon substrate (34) or the leadframe may have a die-attach pad (20) to which is fixed the separate silicon substrate (34). For the cavity-type package (120), the package body includes a mounting surface formed adjacent to a cavity formed therein and the mounting surface has the separate silicon substrate (102) fixed to the top surface thereof. The cavity-type body (120) is formed of a ceramic material or as a multi-layer pringed-circuit board. One or more interposer areas (122) are formed on the top surface of the silicon substrate (102) for attachment of connection wires (125, 127) from the integrated-circuit die (114) or the leadframe (42). A portion of the interposer (72, 122) can extend between the integrated circuit die (32, 114) and the top surface of the silicon substrate (34, 102) to accomodate integrated-circuit dies (32, 114) of various sizes. The interposer includes a layer of oxide (82) formed on the surface of the silicon substrate (34, 102), which layer of oxide is covered with a layer of conductive material (84).

Abstract translation: 集成电路封装组件包括固定有集成电路管芯（32）的单独的硅衬底（34）。 单独的硅衬底（34）用作集成电路管芯（32）的散热器。 集成电路管芯（32）固定到其上的单独的硅衬底（34）封装在模制封装主体（80）或空腔型封装体（120）中。 对于模制封装体（80），封装主体围绕引线框架（42），集成电路管芯（32）和集成电路管芯（32）固定到其上的分离的硅衬底（34） 。 对于模制封装主体（80），引线框架（42）具有形成在其内端的接合指状物，其附接到单独的硅衬底（34），或者引线框架可以具有管芯附接焊盘（20） 固定分离的硅衬底（34）。 对于空腔型封装（120），封装主体包括与形成在其中的空腔相邻形成的安装表面，并且安装表面具有固定到其顶表面的分离的硅衬底（102）。 空腔型主体（120）由陶瓷材料形成，也可以形成为多层布线基板。 在硅衬底（102）的顶表面上形成一个或多个插入区（122），用于从集成电路裸片（114）或引线框架（42）连接连接线（125,127）。 插入器（72,122）的一部分可以在集成电路管芯（32,114）和硅衬底（34,102）的顶表面之间延伸，以容纳各种尺寸的集成电路管芯（32,114）。 插入器包括形成在硅衬底（34,102）的表面上的氧化物层（82），该层的氧化物覆盖有导电材料层（84）。

公开(公告)号：WO1994029899A1

公开(公告)日：1994-12-22

申请号：PCT/US1994005628

申请日：1994-05-19

Applicant: VLSI TECHNOLOGY, INC.

Inventor： VLSI TECHNOLOGY, INC. ,  JAIN, Vivek ,  WELING, Milind, G. ,  PRAMANIK, Dipankar

IPC: H01L21/90

CPC classification number: H01L21/31055 ,  H01L21/76819 ,  Y10S438/97

Abstract: Void-free planarization of sub-micron semiconductor devices results from depositing a layer of silicon-enriched oxide (210) over a conventionally fabricated device and its metal traces (200). Conventional layers of TEOS-based oxide (220) and SOG (230) are then applied over the layer of the silicon-enriched oxide (210). The silicon-enriched oxide has an index of refraction of at least 1.50, a dangling bond density of about 10 /cm , and is about 1000 to 2000 angstroms thick. Because it is relatively deficient in oxygen atoms, the silicon-enriched oxide releases few oxygen atoms when exposed by the etching process and does not greatly accelerate the SOG etch rate. The silicon-enriched oxide has an etch rate that is only about 75 % that of the stoichiometric TEOS-based oxide and it thereby acts as a buffer that slows the etch-back process as the etching approaches the metal traces, thereby protecting the metal traces against exposure. The silicon-enriched oxide promotes stability and reliability of the underlying device by performing a shield-like function in neutralizing charges that could influence the underlying device.

Abstract translation: 通过在常规制造的器件及其金属迹线（200）上沉积富含硅的氧化物层（210），导致亚微米半导体器件的无空间平坦化。 然后将TEOS基氧化物（220）和SOG（230）的常规层施加在富硅氧化物（210）的层上。 富硅氧化物的折射率至少为1.50，悬挂键密度为约10 17 / cm 3，为约1000至2000埃厚。 由于氧原子相对不足，当通过蚀刻工艺暴露时，富硅氧化物释放出很少的氧原子，并且不会极大地加速SOG蚀刻速率。 富硅氧化物的蚀刻速率仅为基于化学计量的TEOS基氧化物的蚀刻速率的约75％，因此其作为缓冲层，当蚀刻接近金属迹线时缓慢地进行回蚀处理，从而保护金属迹线 反对曝光。 富含硅的氧化物通过在中和可能影响底层器件的电荷中进行屏蔽状功能来提高底层器件的稳定性和可靠性。