公开(公告)号：WO2023088115A1

公开(公告)日：2023-05-25

申请号：PCT/CN2022/130259

申请日：2022-11-07

Applicant: 华为技术有限公司

Inventor： 郭小亚

IPC: H01L23/495 ,  H05K1/18

Abstract: 本申请实施例提供一种封装结构、芯片模组、板级架构及通信设备，旨在解决现有技术中应用QFN封装芯片时要设置转接架来传递信号，导致信号传递路径较长、信号损耗大的问题。本实施例提供的封装结构通过将基板、第一引脚阵列、与第一引脚阵列电连接的第二引脚阵列以及至少一个芯片设置于介质层内，且第一引脚阵列的引脚与至少一个芯片中的一个或多个电连接，第二引脚阵列中的每个引脚的至少部分表面裸露在介质层的第二面，当封装结构置于两个外接电路板之间时，第二引脚阵列与一个外接电路板接触并电连接，信号经芯片、第一引脚阵列、第二引脚阵列传输给外接电路板，无需转接架转送信号，信号的传输路径变短，使得信号传输过程中的损耗减小。

公开(公告)号：WO2023044384A1

公开(公告)日：2023-03-23

申请号：PCT/US2022/076487

申请日：2022-09-15

Applicant: MAREL POWER SOLUTIONS, INC.

Inventor： BYERS, Ian ,  MILLER, Gary ,  WOOTERS, Stuart ,  HAREL, Jean-Claude

IPC: H02M7/00 ,  H05K7/20 ,  H01L23/427 ,  H01L23/495

Abstract: A device that includes a printed circuit board (PCB), a metal conductor, and a transistor. The metal conductor includes first and second oppositely facing surfaces. The transistor includes first and second terminals between which current is transmitted when the transistor is activated, and a gate terminal for controlling the transistor. The first terminal is sintered to the first surface, and the gate is electrically connected to a trace on the PCB.

公开(公告)号：WO2023003435A1

公开(公告)日：2023-01-26

申请号：PCT/KR2022/010820

申请日：2022-07-22

Applicant: 엘지이노텍 주식회사

Inventor： 이기한 ,  김상일 ,  라세웅

IPC: H05K3/28 ,  H05K1/11 ,  H01L23/28 ,  H01L23/495

Abstract: 실시 예의 회로 기판은 제1 절연층; 상기 제1 절연층 위에 배치되는 제1 회로 패턴층; 및 상기 제1 절연층 및 상기 제1 회로 패턴층 위에 배치되는 제1 보호층을 포함하고, 상기 제1 회로 패턴층은 제1 패드를 포함하고, 상기 제1 보호층은, 상기 제1 절연층 위에 배치된 제1 부분과, 상기 제1 부분 위에 배치되고, 상기 제1 부분의 상면의 일부 및 상기 제1 패드의 상면을 노출하는 개구부를 가지는 제2 부분을 포함하고, 상기 제2 부분의 측벽에는 내측 방향으로 함몰된 패임부가 형성된다.

公开(公告)号：WO2023279794A1

公开(公告)日：2023-01-12

申请号：PCT/CN2022/086201

申请日：2022-04-12

Applicant: 南京芯干线科技有限公司

Inventor： 傅玥 ,  孔令涛

IPC: H01L23/495 ,  H01L23/49 ,  H01L25/16

Abstract: 提供了一种开关功率器件（10），其特征在于，包括：器件框架（11），在所述器件框架（11）上形成有门极（20）、开尔文源极（30）和漏极（40）；所述门极（20）和开尔文源极（30）设置在所述器件框架（11）的其中一端，所述漏极（40）设置在器件框架（11）的另一端；所述门极（20）和开尔文源极（30）均设置有两个；所述器件框架（11）的其中一端依次设置有所述门极（20）、开尔文源极（30）、开尔文源极（30）和门极（20），以形成对称式管脚结构。使用对称门极设计，就开关功率器件本身而言，让其内部发热更加均衡，提升芯片承受电流的能力的同时带来更好的可靠性。

公开(公告)号：WO2022227027A1

公开(公告)日：2022-11-03

申请号：PCT/CN2021/091579

申请日：2021-04-30

Applicant: 华为技术有限公司

Inventor： 潘伟健 ,  刘闻凤 ,  王海明

IPC: H01L31/0203 ,  H01L25/11 ,  H01L23/00 ,  H01L23/495

Abstract: 本申请涉及半导体技术领域，具体涉及一种空腔封装结构、空腔封装方法及电子设备。空腔封装结构包括基板、外壳和封堵件，其中，基板上具有安装面，安装面用于安装电子器件，外壳安装于基板的安装面上，外壳与基板的安装面之间形成有空腔，电子器件位于空腔中；其中，外壳上设有一个或多个通孔，封堵件与一个或多个通孔匹配，所述封堵件可选择的开启和封堵所述一个或多个通孔。本申请中的空腔封装结构可以使空腔内部与外部气压保持平衡，从而提高封装效果。

公开(公告)号：WO2022214192A1

公开(公告)日：2022-10-13

申请号：PCT/EP2021/059247

申请日：2021-04-09

Applicant: HUAWEI TECHNOLOGIES CO., LTD. ,  HÖGERL, Jürgen

Inventor： HÖGERL, Jürgen

IPC: H01L23/051 ,  H01L23/31 ,  H01L23/367 ,  H01L23/373 ,  H01L23/433 ,  H01L23/495

Abstract: The present disclosure relates to a semiconductor package, comprising: a first substrate, a semiconductor chip, a leadframe; and an encapsulant. A lower main face of the encapsulant comprises a first portion extending in a first plane, a second portion extending in a second plane, a third portion extending in a first transition zone between the first plane and the second plane, and a fourth portion extending in a second transition zone between the second plane and at least one lead. The first portion of the encapsulant and a lower main face of the first substrate are extending in the same first plane forming a lower heat dissipation surface of the package. The second portion, the third portion and the fourth portion of the encapsulant are dimensioned to keep a first predefined minimum distance between the first portion of the encapsulant and the at least one lead.

公开(公告)号：WO2022164620A1

公开(公告)日：2022-08-04

申请号：PCT/US2022/011749

申请日：2022-01-10

Applicant: CREE, INC.

Inventor： SEAL, Sayan ,  SAXENA, Kuldeep ,  BALARAMAN, Devarajan

IPC: H01L23/373 ,  H01L23/433 ,  H01L23/495

Abstract: A packaged electronic device comprises a power semiconductor die that comprises a first terminal and a second terminal, a lead frame comprising a lower side and an upper side that comprises a die pad region, a first lead and a second lead, wherein the first lead is integral with the lead frame and electrically connected to the first terminal of the power semiconductor die through the lead frame, a dielectric substrate, and a thermally conductive adhesion layer on an upper side of the dielectric substrate. The power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the thermally conductive adhesion layer.

公开(公告)号：WO2022101870A1

公开(公告)日：2022-05-19

申请号：PCT/IB2021/060549

申请日：2021-11-15

Applicant: EDA INDUSTRIES S.P.A

Inventor： PALELLA, Fortunato

IPC: H01L21/66 ,  H01L21/67 ,  H01L23/495 ,  G01R31/28

Abstract: The present invention refers to a new process method for the production of electronic semiconductor devices based on the execution of a greater number of production and test steps while the electronic devices are still carried by the Lead Frame.

公开(公告)号：WO2022042998A1

公开(公告)日：2022-03-03

申请号：PCT/EP2021/071322

申请日：2021-07-29

Applicant: HITACHI ENERGY SWITZERLAND AG

Inventor： BEYER, Harald ,  TRUESSEL, Dominik ,  MALEKI, Milad ,  FISCHER, Fabian ,  GADE, Robert

IPC: H01L23/495

Abstract: In one embodiment, the power semiconductor module (1) comprises: - a main substrate (2), - a plurality of first semiconductor chips (3) mounted on the main substrate (2), and - an auxiliary substrate (4) also mounted on the main substrate (2), the auxiliary substrate (4) comprises a top face (40) remote from the main substrate (2), wherein - the auxiliary substrate (4) is a printed circuit board comprising at least one carrier layer (41) which is based on an organic material, and - the auxiliary substrate (4) provides a common contact platform (44) for the first semiconductor chips (3).

公开(公告)号：WO2022021799A1

公开(公告)日：2022-02-03

申请号：PCT/CN2020/141965

申请日：2020-12-31

Applicant: 矽磐微电子（重庆）有限公司

Inventor： 霍炎 ,  涂旭峰

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/498

Abstract: 本申请提供一种半导体封装方法及半导体封装结构。根据一示例，该半导体封装方法包括：将引线框与多个待封装芯片贴装于载板上，且多个待封装芯片位于引线框的镂空区域中；通过将包封层覆盖在待封装芯片、引线框以及载板露出的部分上，且填充于镂空区域内，形成包封结构件；在包封结构件的第一表面形成第一再布线结构，第一再布线结构与待封装芯片的正面以及引线框的第一面均电连接；以及，在包封结构件的第二表面形成第二再布线结构，第二再布线结构与引线框与第一面相对设置的第二面电连接。该半导体封装结构通过该半导体封装方法制得。