公开(公告)号：WO2009073542A1

公开(公告)日：2009-06-11

申请号：PCT/US2008/084939

申请日：2008-11-26

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  JULICHER, Joseph ,  SMIT, Zacharias, Marthinus ,  STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S. ,  ELLISON, Ryan, Scott ,  SCHROEDER, Eric

Inventor： JULICHER, Joseph ,  SMIT, Zacharias, Marthinus ,  STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S. ,  ELLISON, Ryan, Scott ,  SCHROEDER, Eric

IPC: G06F9/46

CPC classification number: G06F9/461

Abstract: A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.

Abstract translation: 微控制器设备具有中央处理单元（CPU）; 与被分成多个存储体的CPU耦合的数据存储器，可以是存储器映射的多个特殊功能寄存器和通用寄存器，其中至少以下特殊功能寄存器被存储器映射到所有存储体：a 状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器; 并且其中在出现上下文切换时，所述CPU可操作以自动保存状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容，并且在返回时 从上下文切换恢复状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容。

公开(公告)号：WO2009073532A1

公开(公告)日：2009-06-11

申请号：PCT/US2008/084921

申请日：2008-11-26

Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  JULICHER, Joseph ,  SMIT, Zacharias, Marthinus ,  STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S. ,  ELLISON, Ryan, Scott ,  SCHROEDER, Eric

Inventor： JULICHER, Joseph ,  SMIT, Zacharias, Marthinus ,  STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S. ,  ELLISON, Ryan, Scott ,  SCHROEDER, Eric

IPC: G06F9/318 ,  G06F9/35

CPC classification number: G06F9/30181 ,  G06F9/35

Abstract: An n-bit microprocessor device has an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, with at least two 16-bit indirect memory address registers which are accessible by the CPU across all banks; a bank access unit for coupling the CPU with one of the plurality of banks; a data memory coupled with the CPU; and a program memory coupled with the CPU, wherein the indirect address registers are operable to access the data memory or program memory and wherein a bit in each of the indirect memory address registers indicates an access to the data memory or to the program memory.

Abstract translation: n位微处理器设备具有n位中央处理单元（CPU）; 多个特殊功能寄存器和通用寄存器，其被存储器映射到多个存储体，具有至少两个16位间接存储器地址寄存器，这些存储器地址寄存器可由所有存储体中的CPU访问; 用于将CPU与多个存储体中的一个耦合的存储单元存取单元; 与CPU耦合的数据存储器; 以及与CPU耦合的程序存储器，其中间接地址寄存器可操作以访问数据存储器或程序存储器，并且其中每个间接存储器地址寄存器中的位指示对数据存储器或程序存储器的访问。