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    CONFIGURABLE LOGIC CELLS
    1.
    发明申请
    CONFIGURABLE LOGIC CELLS 审中-公开
    可配置逻辑电池

    公开(公告)号：WO2012145511A3

    公开(公告)日：2013-02-14

    申请号：PCT/US2012034250

    申请日：2012-04-19

    Applicant: MICROCHIP TECH INC ,  KILZER KEVIN LEE ,  STEEDMAN SEAN ,  ZDENEK JERROLD S ,  DELPORT VIVIEN ,  LUNDSTRUM ZEKE ,  DUVENHAGE FANIE

    Inventor： KILZER KEVIN LEE ,  STEEDMAN SEAN ,  ZDENEK JERROLD S ,  DELPORT VIVIEN ,  LUNDSTRUM ZEKE ,  DUVENHAGE FANIE

    IPC: G06F15/78

    CPC classification number: H03K19/17708 ,  G06F15/7867

    Abstract: An integrated circuit device, in accordance with embodiments as claimed includes a central processing core; and a plurality of peripherals operably coupled to the RISC CPU core. In some embodiments, the plurality of peripherals include at least one configurable logic cell peripheral having more inputs than input-output connections on the integrated circuit device. In some embodiments, the inputs include one or more inputs from one or more integrated circuit subsystems.

    Abstract translation: 根据权利要求的实施例的集成电路装置包括中央处理核心; 以及可操作地耦合到RISC CPU核心的多个外围设备。 在一些实施例中，多个外围设备包括具有比集成电路设备上的输入 - 输出连接更多的输入的至少一个可配置逻辑单元外围设备。 在一些实施例中，输入包括来自一个或多个集成电路子系统的一个或多个输入。

    REGULATOR BYPASS START-UP IN AN INTEGRATED CIRCUIT DEVICE
    7.
    发明申请
    REGULATOR BYPASS START-UP IN AN INTEGRATED CIRCUIT DEVICE 审中-公开
    集成电路设备中的调节器旁路启动

    公开(公告)号：WO2008137707A1

    公开(公告)日：2008-11-13

    申请号：PCT/US2008/062455

    申请日：2008-05-02

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S. ,  LOURENS, Ruan ,  CHARLES, Michael ,  JULICHER, Joseph ,  SCHROEDER, Eric

    Inventor： STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S. ,  LOURENS, Ruan ,  CHARLES, Michael ,  JULICHER, Joseph ,  SCHROEDER, Eric

    IPC: G11C5/14 ,  G05F1/46

    CPC classification number: G11C5/147

    Abstract: An internal' voltage regulator (108) in an integrated circuit device (102) is always active upon initial start-up and/or power-on-reset operations. The internal voltage regulator (108) protects the low voltage core logic circuits (104, 106) of the integrated circuit device (102) from excessively high voltages that may be present in a particular application. In addition, nonvolatile memory (104) may be part of and operational with the low voltage core logic circuits (104, 106) for storing device operating parameters. Therefore, the internal voltage regulator (108) also protects the low voltage nonvolatile memory (104) from excessive high voltages. Once the integrated circuit device (102) has stabilized and all logic circuits therein fully function, a bit(s) in the nonvolatile memory (104) may be read to determine if the internal voltage regulator (108) should remain active, e.g., power operation with a high voltage source, or be placed into a bypass mode for low power operation when the integrated circuit device (102) is powered by a low voltage.

    Abstract translation: 在初始启动和/或上电复位操作时，集成电路器件（102）中的内部“稳压器（108）”总是有效。 内部电压调节器（108）保护集成电路器件（102）的低电压核心逻辑电路（104,106）免受可能存在于特定应用中的过高的电压。 此外，非易失性存储器（104）可以是用于存储设备操作参数的低电压核心逻辑电路（104,106）的一部分并且可操作。 因此，内部稳压器（108）也保护低压非易失性存储器（104）免受过高的高电压的影响。 一旦集成电路器件（102）已经稳定并且其中的所有逻辑电路完全起作用，则可以读取非易失性存储器（104）中的位以确定内部稳压器（108）是否应该保持有效，例如功率 当集成电路器件（102）由低电压供电时，用高电压源操作或被置于旁路模式以进行低功率操作。

    MODULATOR MODULE IN AN INTEGRATED CIRCUIT DEVICE
    8.
    发明申请
    MODULATOR MODULE IN AN INTEGRATED CIRCUIT DEVICE 审中-公开
    集成电路设备中的调制器模块

    公开(公告)号：WO2010085721A1

    公开(公告)日：2010-07-29

    申请号：PCT/US2010/021915

    申请日：2010-01-25

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  LUNDSTRUM, Zeke, R. ,  CURTIS, Keith ,  STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S.

    Inventor： LUNDSTRUM, Zeke, R. ,  CURTIS, Keith ,  STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S.

    IPC: H03C3/00 ,  H04L27/12 ,  H05B41/392

    CPC classification number: H03C3/00 ,  H04L27/122 ,  H05B41/2828

    Abstract: An integrated circuit device has a modulator module that provides a modulation signal comprising one frequency keyed on and off, or alternating between two or more different frequencies or phases that are selected based upon a modulator signal. The one or more frequencies or phases may be selected from a plurality of frequency sources. Switching the one frequency on or off, or between the at least two different frequencies or phases may be synchronized with one or both of the two or more different frequencies or phases so that "glitches" or spurs are not introduced into the modulation signal. The integrated circuit device may also comprise a processor, memory, digital logic and input-output. Frequency sources may be internal to the digital device or external. The modulator signal may comprise serial data generated from the digital logic and/or processor of the digital device.

    Abstract translation: 集成电路装置具有调制器模块，该调制器模块提供包括基于调制器信号选择的一个频率键控开关或交替的两个或多个不同频率或相位之间的调制信号。 可以从多个频率源中选择一个或多个频率或相位。 将一个频率开启或关闭，或者在至少两个不同频率或相位之间切换可以与两个或更多个不同频率或相位中的一个或两个同步，使得“毛刺”或杂散不被引入到调制信号中。 集成电路设备还可以包括处理器，存储器，数字逻辑和输入 - 输出。 频率源可能在数字设备内部或外部。 调制器信号可以包括从数字设备的数字逻辑和/或处理器产生的串行数据。

    ENHANCED MICROPROCESSOR OR MICROCONTROLLER
    9.
    发明申请
    ENHANCED MICROPROCESSOR OR MICROCONTROLLER 审中-公开
    增强微处理器或MICROCONTROLLER

    公开(公告)号：WO2009073532A1

    公开(公告)日：2009-06-11

    申请号：PCT/US2008/084921

    申请日：2008-11-26

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  JULICHER, Joseph ,  SMIT, Zacharias, Marthinus ,  STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S. ,  ELLISON, Ryan, Scott ,  SCHROEDER, Eric

    Inventor： JULICHER, Joseph ,  SMIT, Zacharias, Marthinus ,  STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S. ,  ELLISON, Ryan, Scott ,  SCHROEDER, Eric

    IPC: G06F9/318 ,  G06F9/35

    CPC classification number: G06F9/30181 ,  G06F9/35

    Abstract: An n-bit microprocessor device has an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, with at least two 16-bit indirect memory address registers which are accessible by the CPU across all banks; a bank access unit for coupling the CPU with one of the plurality of banks; a data memory coupled with the CPU; and a program memory coupled with the CPU, wherein the indirect address registers are operable to access the data memory or program memory and wherein a bit in each of the indirect memory address registers indicates an access to the data memory or to the program memory.

    Abstract translation: n位微处理器设备具有n位中央处理单元（CPU）; 多个特殊功能寄存器和通用寄存器，其被存储器映射到多个存储体，具有至少两个16位间接存储器地址寄存器，这些存储器地址寄存器可由所有存储体中的CPU访问; 用于将CPU与多个存储体中的一个耦合的存储单元存取单元; 与CPU耦合的数据存储器; 以及与CPU耦合的程序存储器，其中间接地址寄存器可操作以访问数据存储器或程序存储器，并且其中每个间接存储器地址寄存器中的位指示对数据存储器或程序存储器的访问。

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