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    ENHANCED MICROPROCESSOR OR MICROCONTROLLER
    1.
    发明申请
    ENHANCED MICROPROCESSOR OR MICROCONTROLLER 审中-公开
    增强微处理器或MICROCONTROLLER

    公开(公告)号：WO2009073532A1

    公开(公告)日：2009-06-11

    申请号：PCT/US2008/084921

    申请日：2008-11-26

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  JULICHER, Joseph ,  SMIT, Zacharias, Marthinus ,  STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S. ,  ELLISON, Ryan, Scott ,  SCHROEDER, Eric

    Inventor： JULICHER, Joseph ,  SMIT, Zacharias, Marthinus ,  STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S. ,  ELLISON, Ryan, Scott ,  SCHROEDER, Eric

    IPC: G06F9/318 ,  G06F9/35

    CPC classification number: G06F9/30181 ,  G06F9/35

    Abstract: An n-bit microprocessor device has an n-bit central processing unit (CPU); a plurality of special function registers and general purpose registers which are memory-mapped to a plurality of banks, with at least two 16-bit indirect memory address registers which are accessible by the CPU across all banks; a bank access unit for coupling the CPU with one of the plurality of banks; a data memory coupled with the CPU; and a program memory coupled with the CPU, wherein the indirect address registers are operable to access the data memory or program memory and wherein a bit in each of the indirect memory address registers indicates an access to the data memory or to the program memory.

    Abstract translation: n位微处理器设备具有n位中央处理单元（CPU）; 多个特殊功能寄存器和通用寄存器，其被存储器映射到多个存储体，具有至少两个16位间接存储器地址寄存器，这些存储器地址寄存器可由所有存储体中的CPU访问; 用于将CPU与多个存储体中的一个耦合的存储单元存取单元; 与CPU耦合的数据存储器; 以及与CPU耦合的程序存储器，其中间接地址寄存器可操作以访问数据存储器或程序存储器，并且其中每个间接存储器地址寄存器中的位指示对数据存储器或程序存储器的访问。

    USER SELECTABLE PIN FOR CONNECTION OF AN INTERNAL REGULATOR TO AN EXTERNAL FILTER/STABILIZATION CAPACITOR AND PREVENTION OF A CURRENT SURGE THEREBETWEEN
    4.
    发明申请
    USER SELECTABLE PIN FOR CONNECTION OF AN INTERNAL REGULATOR TO AN EXTERNAL FILTER/STABILIZATION CAPACITOR AND PREVENTION OF A CURRENT SURGE THEREBETWEEN 审中-公开
    用于将内部稳压器连接到外部滤波器/稳压电容器的用户可选择的引脚，并防止其中的电流浪涌

    公开(公告)号：WO2008137725A1

    公开(公告)日：2008-11-13

    申请号：PCT/US2008/062477

    申请日：2008-05-02

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  HULL, Richard ,  DELPORT, Vivien ,  SMIT, Zacharias, Marthinus ,  STEEDMAN, Sean ,  ZDENEK, Jerrold, S. ,  CHARLES, Michael ,  LOURENS, Ruan

    Inventor： HULL, Richard ,  DELPORT, Vivien ,  SMIT, Zacharias, Marthinus ,  STEEDMAN, Sean ,  ZDENEK, Jerrold, S. ,  CHARLES, Michael ,  LOURENS, Ruan

    IPC: G05F1/46 ,  H01L27/00

    CPC classification number: G11C5/147 ,  Y10T307/74 ,  Y10T307/747 ,  Y10T307/858

    Abstract: An integrated circuit device provides a choice of external pins (connections) that may be user selectable for coupling an external filter/stabilization capacitor to an internal voltage regulator. However, connecting the output of a internal voltage regulator to an uncharged external filter/stabilization capacitor (or to a capacitor charged to a different voltage level than the internal regulation voltage) through a low impedance path can cause the regulator output voltage to sag/spike if the internal voltage regulator tries to charge/discharge the capacitor up/down to equilibrium with the regulator output voltage. To minimize this potential sag/spike, the voltage on the external filter/stabilization capacitor may be adjusted in a controlled manner to substantially the same voltage as the voltage on the output of the internal voltage regulator, and then the internal voltage regulator is operationally coupled through a low impedance to the external regulator filter/stabilization capacitor.

    Abstract translation: 集成电路器件提供可选择用于外部滤波器/稳定电容器耦合到内部稳压器的外部引脚（连接）的选择。 然而，通过低阻抗路径将内部稳压器的输出连接到不带电的外部滤波器/稳定电容器（或者与内部调节电压相比，被充电到不同电压电平的电容器）可能会导致稳压器输出电压下垂/尖峰 如果内部电压调节器试图将电容器上/下放电到稳压器输出电压的平衡。 为了最小化该潜在的下垂/尖峰，可以以受控的方式将外部滤波器/稳定电容器上的电压调节到与内部稳压器的输出端上的电压基本相同的电压，然后内部电压调节器可操作地耦合 通过低阻抗到外部调节滤波器/稳定电容器。

    ENHANCED MICROPROCESSOR OR MICROCONTROLLER
    6.
    发明申请
    ENHANCED MICROPROCESSOR OR MICROCONTROLLER 审中-公开
    增强微处理器或MICROCONTROLLER

    公开(公告)号：WO2009073542A1

    公开(公告)日：2009-06-11

    申请号：PCT/US2008/084939

    申请日：2008-11-26

    Applicant: MICROCHIP TECHNOLOGY INCORPORATED ,  JULICHER, Joseph ,  SMIT, Zacharias, Marthinus ,  STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S. ,  ELLISON, Ryan, Scott ,  SCHROEDER, Eric

    Inventor： JULICHER, Joseph ,  SMIT, Zacharias, Marthinus ,  STEEDMAN, Sean ,  DELPORT, Vivien ,  ZDENEK, Jerrold, S. ,  ELLISON, Ryan, Scott ,  SCHROEDER, Eric

    IPC: G06F9/46

    CPC classification number: G06F9/461

    Abstract: A microcontroller device has a central processing unit (CPU); a data memory coupled with the CPU divided into a plurality of memory banks, a plurality of special function registers and general purpose registers which may be memory-mapped, wherein at least the following special function registers are memory-mapped to all memory banks: a status register, a bank select register, a plurality of indirect memory address registers, a working register, and a program counter high latch; and wherein upon occurrence of a context switch, the CPU is operable to automatically save the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch, and upon return from the context switch restores the content of the status register, the bank select register, the plurality of indirect memory address registers, the working register, and the program counter high latch.

    Abstract translation: 微控制器设备具有中央处理单元（CPU）; 与被分成多个存储体的CPU耦合的数据存储器，可以是存储器映射的多个特殊功能寄存器和通用寄存器，其中至少以下特殊功能寄存器被存储器映射到所有存储体：a 状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器; 并且其中在出现上下文切换时，所述CPU可操作以自动保存状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容，并且在返回时 从上下文切换恢复状态寄存器，存储体选择寄存器，多个间接存储器地址寄存器，工作寄存器和程序计数器高锁存器的内容。

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