公开(公告)号：WO2013003159A2

公开(公告)日：2013-01-03

申请号：PCT/US2012043407

申请日：2012-06-20

Applicant: INTEL CORP ,  BURNS JAMES S ,  GANESAN BASKARAN ,  FENGER RUSSELL J ,  BODAS DEVADATTA V ,  IYENGAR SUNDARAVARATHAN R ,  NELSON FERANAK ,  POWELL JOHN M JR ,  SUGUMAR SURESH

Inventor： BURNS JAMES S ,  GANESAN BASKARAN ,  FENGER RUSSELL J ,  BODAS DEVADATTA V ,  IYENGAR SUNDARAVARATHAN R ,  NELSON FERANAK ,  POWELL JOHN M JR ,  SUGUMAR SURESH

CPC classification number: G06F1/3287 ,  G06F1/26 ,  G06F1/329 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/24

Abstract: In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器具有多个核以执行线程。 处理器还包括功率控制逻辑，用于基于存储核心功率的计数的计数器的阈值和值与识别至少一个线程的turbo模式请求的性能组合之间的比较，使得能够进入turbo模式。 以这种方式，可以在提供高功率效率的处理器的利用水平下输入涡轮模式。 描述并要求保护其他实施例。

公开(公告)号：WO2014105150A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/046907

申请日：2013-06-20

Applicant: INTEL CORPORATION ,  CONRAD, Shaun M. ,  FENGER, Russell J. ,  KHANNA, Gaurav ,  SETH, Rahul ,  CROSSLAND, James B. ,  AGGARWAL, Anil

Inventor： CONRAD, Shaun M. ,  FENGER, Russell J. ,  KHANNA, Gaurav ,  SETH, Rahul ,  CROSSLAND, James B. ,  AGGARWAL, Anil

IPC: G06F9/38 ,  G06F9/46 ,  G06F12/10

CPC classification number: G06F12/1027 ,  G06F1/3206 ,  G06F2212/683 ,  Y02D10/13

Abstract: A method is described that includes recognizing that TLB information of one or more hardware threads is to be invalidated. The method also includes determining which ones of the one or more hardware threads are in a state in which TLB information is flushed. The method also includes directing a TLB shootdown to those of the or more hardware threads that are in a state in which TLB information is not flushed.

Abstract translation: 描述了包括识别一个或多个硬件线程的TLB信息被无效的方法。 该方法还包括确定一个或多个硬件线程中的哪一个处于其中刷新TLB信息的状态。 该方法还包括将TLB拍摄定向到处于未刷新TLB信息的状态的那些或更多个硬件线程。

公开(公告)号：WO2014105145A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/046634

申请日：2013-06-19

Applicant: INTEL CORPORATION ,  NARVAEZ, Paolo ,  SRINIVASA, Ganapati N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David A. ,  BRETT, Paul ,  HAHN, Scott D. ,  HERDRICH, Andrew J. ,  IYER, Ravishankar ,  CHITLUR, Nagabhushan ,  SODHI, Inder M. ,  KHANNA, Gaurav ,  FENGER, Russell J.

Inventor： NARVAEZ, Paolo ,  SRINIVASA, Ganapati N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David A. ,  BRETT, Paul ,  HAHN, Scott D. ,  HERDRICH, Andrew J. ,  IYER, Ravishankar ,  CHITLUR, Nagabhushan ,  SODHI, Inder M. ,  KHANNA, Gaurav ,  FENGER, Russell J.

IPC: G06F9/28 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/5044 ,  G06F9/45533 ,  G06F9/5077 ,  G06F9/5094 ,  G06F15/80 ,  Y02D10/22

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a first set of one or more physical processor cores having first processing characteristics; a second set of one or more physical processor cores having second processing characteristics different from the first processing characteristics; virtual-to-physical (V-P) mapping logic to expose a plurality of virtual processors to software, the plurality of virtual processors to appear to the software as a plurality of homogeneous processor cores, the software to allocate threads to the virtual processors as if the virtual processors were homogeneous processor cores; wherein the V-P mapping logic is to map each virtual processor to a physical processor within the first set of physical processor cores or the second set of physical processor cores such that a thread allocated to a first virtual processor by software is executed by a physical processor mapped to the first virtual processor from the first set or the second set of physical processors.

Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：具有第一处理特性的一个或多个物理处理器核心的第一组; 具有不同于所述第一处理特性的第二处理特性的第二组一个或多个物理处理器核; 虚拟到物理（VP）映射逻辑，以将多个虚拟处理器暴露给软件，所述多个虚拟处理器将软件呈现为多个同构的处理器核，所述软件将线程分配给虚拟处理器，如同 虚拟处理器是同类处理器核心; 其中所述VP映射逻辑将每个虚拟处理器映射到所述第一物理处理器核心集合或所述第二物理处理器核心集合内的物理处理器，使得通过软件分配给第一虚拟处理器的线程由物理处理器映射执行 从第一组或第二组物理处理器到第一虚拟处理器。

公开(公告)号：WO2013090379A1

公开(公告)日：2013-06-20

申请号：PCT/US2012/069164

申请日：2012-12-12

Applicant: INTEL CORPORATION ,  SCHLUESSLER, Travis T. ,  FENGER, Russell J.

Inventor： SCHLUESSLER, Travis T. ,  FENGER, Russell J.

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/28

CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3253 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/50 ,  G06F9/5094 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24

Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

Abstract translation: 这里描述了一种装置，方法和系统，用于基于测量的工作负载有效地平衡处理元件之间的性能和功率。 如果处理元件的工作负载表明它是瓶颈，则可能会增加其性能。 然而，如果包括处理元件的平台或集成电路已经在功率或热限制下运行，则性能的提高通过另一处理元件的性能的降低或上限来平衡，以保持与功率或热限制的一致性。 因此，即使在多个处理元件在功率或热限制下工作时，通过平衡功率分配来识别和缓解瓶颈。

公开(公告)号：WO2013003159A3

公开(公告)日：2013-01-03

申请号：PCT/US2012/043407

申请日：2012-06-20

Applicant: INTEL CORPORATION ,  BURNS, James S. ,  GANESAN, Baskaran ,  FENGER, Russell J. ,  BODAS, Devadatta V. ,  IYENGAR, Sundaravarathan R. ,  NELSON, Feranak ,  POWELL, John M., Jr. ,  SUGUMAR, Suresh

Inventor： BURNS, James S. ,  GANESAN, Baskaran ,  FENGER, Russell J. ,  BODAS, Devadatta V. ,  IYENGAR, Sundaravarathan R. ,  NELSON, Feranak ,  POWELL, John M., Jr. ,  SUGUMAR, Suresh

IPC: G06F1/00 ,  G06F1/26 ,  G06F9/06

Abstract: In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.

公开(公告)号：WO2014105175A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/047706

申请日：2013-06-25

Applicant: INTEL CORPORATION ,  GORBATOV, Eugene ,  NAVEH, Alon ,  SODHI, Inder M. ,  SRINIVASA, Ganapati N. ,  WEISSMANN, Eliezer ,  KHANNA, Gaurav ,  NAIK, Mishali ,  FENGER, Russell J. ,  HENROID, Andrew D. ,  SUBBAREDDY, Dheeraj R. ,  KOUFATY, David A. ,  NARVAEZ, Paolo

Inventor： GORBATOV, Eugene ,  NAVEH, Alon ,  SODHI, Inder M. ,  SRINIVASA, Ganapati N. ,  WEISSMANN, Eliezer ,  KHANNA, Gaurav ,  NAIK, Mishali ,  FENGER, Russell J. ,  HENROID, Andrew D. ,  SUBBAREDDY, Dheeraj R. ,  KOUFATY, David A. ,  NARVAEZ, Paolo

IPC: G06F9/28 ,  G06F9/38 ,  G06F9/46

CPC classification number: G06F9/5094 ,  G06F1/206 ,  G06F1/3206 ,  Y02D10/16 ,  Y02D10/22

Abstract: A processor of an aspect includes at least one lower processing capability and lower power consumption physical compute element and at least one higher processing capability and higher power consumption physical compute element. Migration performance benefit evaluation logic is to evaluate a performance benefit of a migration of a workload from the at least one lower processing capability compute element to the at least one higher processing capability compute element, and to determine whether or not to allow the migration based on the evaluated performance benefit. Available energy and thermal budget evaluation logic is to evaluate available energy and thermal budgets and to determine to allow the migration if the migration fits within the available energy and thermal budgets. Workload migration logic is to perform the migration when allowed by both the migration performance benefit evaluation logic and the available energy and thermal budget evaluation logic.

Abstract translation: 一方面的处理器包括至少一个较低处理能力和较低功耗物理计算元件以及至少一个较高处理能力和较高功耗物理计算元件。 迁移性能优势评估逻辑是评估工作负载从至少一个较低处理能力计算元素迁移到至少一个较高处理能力计算元件的性能优点，并且基于以下步骤确定是否允许基于 评估性能好处。 可用的能源和热力预算评估逻辑是评估可用的能源和热预算，并确定如果迁移符合可用能源和热力预算，则允许迁移。 工作负载迁移逻辑是在迁移性能优势评估逻辑和可用的能源和热预算评估逻辑允许时执行迁移。

公开(公告)号：WO2013006511A2

公开(公告)日：2013-01-10

申请号：PCT/US2012045154

申请日：2012-06-30

Applicant: INTEL CORP ,  GANESAN BASKARAN ,  BURNS JAMES S ,  SUGUMAR SURESH ,  BODAS DEVADATTA V ,  IYENGAR SUNDARAVARATHAN R ,  NELSON FERANAK ,  NAGARAJ DHEEMANTH ,  FENGER RUSSELL J

Inventor： GANESAN BASKARAN ,  BURNS JAMES S ,  SUGUMAR SURESH ,  BODAS DEVADATTA V ,  IYENGAR SUNDARAVARATHAN R ,  NELSON FERANAK ,  NAGARAJ DHEEMANTH ,  FENGER RUSSELL J

CPC classification number: G06F1/324 ,  G06F1/08 ,  Y02D10/126

Abstract: Systems and methods of operating a computing system may involve identifying a plurality of state values, wherein each state value corresponds to a computing thread associated with a processor. An average value can be determined for the plurality of state values, wherein a determination may be made as to whether to grant a frequency boost request based at least in part on the average value.

Abstract translation: 操作计算系统的系统和方法可以涉及识别多个状态值，其中每个状态值对应于与处理器相关联的计算线程。 可以针对多个状态值确定平均值，其中可以至少部分地基于平均值来确定是否授予频率提升请求。

公开(公告)号：WO2014105174A1

公开(公告)日：2014-07-03

申请号：PCT/US2013/047700

申请日：2013-06-25

Applicant: INTEL CORPORATION ,  NARVAEZ, Paolo ,  SRINIVASA, Ganapati, N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj, R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David, A. ,  BRETT, Paul ,  HAHN, Scott, D. ,  HERDRICH, Andrew, J. ,  KHANNA, Gaurav ,  FENGER, Russell, J. ,  BIGBEE, Bryant, E. ,  HENROID, Andrew, D.

Inventor： NARVAEZ, Paolo ,  SRINIVASA, Ganapati, N. ,  GORBATOV, Eugene ,  SUBBAREDDY, Dheeraj, R. ,  NAIK, Mishali ,  NAVEH, Alon ,  PRABHAKARAN, Abirami ,  WEISSMANN, Eliezer ,  KOUFATY, David, A. ,  BRETT, Paul ,  HAHN, Scott, D. ,  HERDRICH, Andrew, J. ,  KHANNA, Gaurav ,  FENGER, Russell, J. ,  BIGBEE, Bryant, E. ,  HENROID, Andrew, D.

IPC: G06F9/44

CPC classification number: G06F9/45558 ,  G06F9/3885 ,  G06F9/5077 ,  G06F2009/4557

Abstract: A heterogeneous processor architecture is described. For example, a processor according to one embodiment of the invention comprises: a set of two or more small physical processor cores; at least one large physical processor core having relatively higher performance processing capabilities and relatively higher power usage relative to the small physical processor cores; virtual-to-physical (V-P) mapping logic to expose the set of two or more small physical processor cores to software through a corresponding set of virtual cores and to hide the at least one large physical processor core from the software.

Abstract translation: 描述异构处理器架构。 例如，根据本发明的一个实施例的处理器包括：一组两个或更多个小物理处理器核; 至少一个大型物理处理器核具有相对较高性能的处理能力和相对较小的物理处理器核的相对较高的功率使用; 虚拟到物理（V-P）映射逻辑，以通过相应的一组虚拟核心将两个或更多个小型物理处理器核心的集合暴露给软件，并从软件中隐藏至少一个大型物理处理器核心。

公开(公告)号：WO2014105058A1

公开(公告)日：2014-07-03

申请号：PCT/US2012/072135

申请日：2012-12-28

Applicant: INTEL CORPORATION ,  SUBBAREDDY, Dheeraj R. ,  SRINIVASA, Ganapati N. ,  KOUFATY, David A. ,  HAHN, Scott D. ,  NAIK, Mishali ,  NARVAEZ, Paolo ,  PRABHAKARAN, Abirami ,  GORBATOV, Eugene ,  NAVEH, Alon ,  SODHI, Inder M. ,  WEISSMANN, Eliezer ,  BRETT, Paul ,  KHANNA, Gaurav ,  FENGER, Russell J.

Inventor： SUBBAREDDY, Dheeraj R. ,  SRINIVASA, Ganapati N. ,  KOUFATY, David A. ,  HAHN, Scott D. ,  NAIK, Mishali ,  NARVAEZ, Paolo ,  PRABHAKARAN, Abirami ,  GORBATOV, Eugene ,  NAVEH, Alon ,  SODHI, Inder M. ,  WEISSMANN, Eliezer ,  BRETT, Paul ,  KHANNA, Gaurav ,  FENGER, Russell J.

IPC: G06F9/06 ,  G06F1/32 ,  G06F9/46 ,  G06F9/44

CPC classification number: G06F9/3885 ,  G06F9/5094 ,  Y02D10/22

Abstract: A processor includes multiple physical cores that support multiple logical cores of different core types, where the core types include a big core type and a small core type. A multi-threaded application includes multiple software threads are concurrently executed by a first subset of logical cores in a first time slot. Based on data gathered from monitoring the execution in the first time slot, the processor selects a second subset of logical cores for concurrent execution of the software threads in a second time slot. Each logical core in the second subset has one of the core types that matches the characteristics of one of the software threads.

Abstract translation: 处理器包括多个物理核，其支持不同核心类型的多个逻辑核，其中核心类型包括大型核心类型和小型核心类型。 多线程应用程序包括多个软件线程，由第一时隙中的逻辑核心的第一子集同时执行。 基于从监视第一时隙中的执行收集的数据，处理器在第二时隙中选择用于并行执行软件线程的逻辑核心的第二子集。 第二子集中的每个逻辑核心具有与其中一个软件线程的特征相匹配的核心类型之一。

公开(公告)号：WO2013006511A3

公开(公告)日：2013-01-10

申请号：PCT/US2012/045154

申请日：2012-06-30

Applicant: INTEL CORPORATION ,  GANESAN, Baskaran ,  BURNS, James, S. ,  SUGUMAR, Suresh ,  BODAS, Devadatta V. ,  IYENGAR, Sundaravarathan, R. ,  NELSON, Feranak ,  NAGARAJ, Dheemanth ,  FENGER, Russell, J.

Inventor： GANESAN, Baskaran ,  BURNS, James, S. ,  SUGUMAR, Suresh ,  BODAS, Devadatta V. ,  IYENGAR, Sundaravarathan, R. ,  NELSON, Feranak ,  NAGARAJ, Dheemanth ,  FENGER, Russell, J.

IPC: G06F9/06

Abstract: Systems and methods of operating a computing system may involve identifying a plurality of state values, wherein each state value corresponds to a computing thread associated with a processor. An average value can be determined for the plurality of state values, wherein a determination may be made as to whether to grant a frequency boost request based at least in part on the average value.