公开(公告)号：WO2013003159A3

公开(公告)日：2013-01-03

申请号：PCT/US2012/043407

申请日：2012-06-20

Applicant: INTEL CORPORATION ,  BURNS, James S. ,  GANESAN, Baskaran ,  FENGER, Russell J. ,  BODAS, Devadatta V. ,  IYENGAR, Sundaravarathan R. ,  NELSON, Feranak ,  POWELL, John M., Jr. ,  SUGUMAR, Suresh

Inventor： BURNS, James S. ,  GANESAN, Baskaran ,  FENGER, Russell J. ,  BODAS, Devadatta V. ,  IYENGAR, Sundaravarathan R. ,  NELSON, Feranak ,  POWELL, John M., Jr. ,  SUGUMAR, Suresh

IPC: G06F1/00 ,  G06F1/26 ,  G06F9/06

Abstract: In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.

公开(公告)号：WO2013006511A3

公开(公告)日：2013-01-10

申请号：PCT/US2012/045154

申请日：2012-06-30

Applicant: INTEL CORPORATION ,  GANESAN, Baskaran ,  BURNS, James, S. ,  SUGUMAR, Suresh ,  BODAS, Devadatta V. ,  IYENGAR, Sundaravarathan, R. ,  NELSON, Feranak ,  NAGARAJ, Dheemanth ,  FENGER, Russell, J.

Inventor： GANESAN, Baskaran ,  BURNS, James, S. ,  SUGUMAR, Suresh ,  BODAS, Devadatta V. ,  IYENGAR, Sundaravarathan, R. ,  NELSON, Feranak ,  NAGARAJ, Dheemanth ,  FENGER, Russell, J.

IPC: G06F9/06

Abstract: Systems and methods of operating a computing system may involve identifying a plurality of state values, wherein each state value corresponds to a computing thread associated with a processor. An average value can be determined for the plurality of state values, wherein a determination may be made as to whether to grant a frequency boost request based at least in part on the average value.

公开(公告)号：WO2012005938A2

公开(公告)日：2012-01-12

申请号：PCT/US2011041228

申请日：2011-06-21

Applicant: INTEL CORP ,  RANGARAJAN THANUNATHAN ,  GANESAN BASKARAN ,  BHATTACHARAYYA BINATA

Inventor： RANGARAJAN THANUNATHAN ,  GANESAN BASKARAN ,  BHATTACHARAYYA BINATA

IPC: G06F11/07 ,  G06F9/46 ,  G06F12/08

CPC classification number: G06F11/1666 ,  G06F11/1658 ,  G06F11/20 ,  G06F12/0813 ,  G06F12/0846 ,  G06F12/0864

Abstract: A semiconductor chip is described having different instances of cache agent logic circuitry for respective cache slices of a distributed cache. The semiconductor chip further includes hash engine logic circuitry comprising: hash logic circuitry to determine, based on an address, that a particular one of the cache slices is to receive a request having the address, and, a first input to receive notice of a failure event for the particular cache slice. The semiconductor chip also includes first circuitry to assign the address to another cache slice of the cache slices in response to the notice.

Abstract translation: 描述了具有用于分布式高速缓存的各个缓存片段的高速缓存代理逻辑电路的不同实例的半导体芯片。 半导体芯片还包括散列引擎逻辑电路，包括：散列逻辑电路，用于基于地址确定特定的一个高速缓存片段将接收具有该地址的请求，以及第一输入以接收故障通知 特定缓存片段的事件。 半导体芯片还包括响应于通知将地址分配给高速缓存片的另一高速缓存片的第一电路。

公开(公告)号：WO2009082320A1

公开(公告)日：2009-07-02

申请号：PCT/SE2008/000703

申请日：2008-12-15

Applicant: GENERAL ELECTRIC COMPANY ,  GE HEALTHCARE BIO-SCIENCES AB ,  GANESAN, Baskaran ,  NATH, Shridhar ,  NORDBERG, Roger ,  RADEBACH, Matthew ,  SUN, Zongqi ,  TOGO, Mottito ,  WILLIAMS, Alan, M.

Inventor： GANESAN, Baskaran ,  NATH, Shridhar ,  NORDBERG, Roger ,  RADEBACH, Matthew ,  SUN, Zongqi ,  TOGO, Mottito ,  WILLIAMS, Alan, M.

IPC: G01N29/024 ,  G01N29/032 ,  G01N29/036 ,  G01N30/02

CPC classification number: G01N30/56 ,  G01N15/06 ,  G01N29/024 ,  G01N2030/565 ,  G01N2291/02416 ,  G01N2291/045

Abstract: A device, method and system for measuring one or more ultrasound parameters of a suspension comprising particles dispersed in a liquid carrier comprising, an immersible devices, comprising, one or more ultrasonic probes; a reflector having staggered reflective; a housing having an opening into the housing to allow the suspension to flow into the space between the probe surface and the reflective surface; an ultrasound wave generator/receiver device; and a signal processing device.

Abstract translation: 一种用于测量悬浮液的一个或多个超声参数的装置，方法和系统，所述悬浮液包含分散在液体载体中的颗粒，所述液体载体包括浸没装置， 具有交错反射的反射器; 壳体，其具有通向所述壳体的开口，以允许所述悬架流入所述探针表面和所述反射表面之间的空间; 超声波发生器/接收器装置; 和信号处理装置。

公开(公告)号：WO2013006511A2

公开(公告)日：2013-01-10

申请号：PCT/US2012045154

申请日：2012-06-30

Applicant: INTEL CORP ,  GANESAN BASKARAN ,  BURNS JAMES S ,  SUGUMAR SURESH ,  BODAS DEVADATTA V ,  IYENGAR SUNDARAVARATHAN R ,  NELSON FERANAK ,  NAGARAJ DHEEMANTH ,  FENGER RUSSELL J

Inventor： GANESAN BASKARAN ,  BURNS JAMES S ,  SUGUMAR SURESH ,  BODAS DEVADATTA V ,  IYENGAR SUNDARAVARATHAN R ,  NELSON FERANAK ,  NAGARAJ DHEEMANTH ,  FENGER RUSSELL J

CPC classification number: G06F1/324 ,  G06F1/08 ,  Y02D10/126

Abstract: Systems and methods of operating a computing system may involve identifying a plurality of state values, wherein each state value corresponds to a computing thread associated with a processor. An average value can be determined for the plurality of state values, wherein a determination may be made as to whether to grant a frequency boost request based at least in part on the average value.

Abstract translation: 操作计算系统的系统和方法可以涉及识别多个状态值，其中每个状态值对应于与处理器相关联的计算线程。 可以针对多个状态值确定平均值，其中可以至少部分地基于平均值来确定是否授予频率提升请求。

公开(公告)号：WO2012166207A1

公开(公告)日：2012-12-06

申请号：PCT/US2011/067984

申请日：2011-12-29

Applicant: INTEL CORPORATION ,  BALASUBRAMANIAN, Srikanth ,  THOMAS, Tessil ,  SHRIMALI, Satish ,  GANESAN, Baskaran

Inventor： BALASUBRAMANIAN, Srikanth ,  THOMAS, Tessil ,  SHRIMALI, Satish ,  GANESAN, Baskaran

IPC: G06F1/32 ,  G06F1/04 ,  G06F15/80

CPC classification number: G06F1/3293 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  Y02D10/128 ,  Y02D50/20

Abstract: In one embodiment, a multi-core processor includes multiple cores and an uncore, where the uncore includes various logic units including a cache memory, a router, and a power control unit (PCU). The PCU can clock gate at least one of the logic units and the cache memory when the multi-core processor is in a low power state to thus reduce dynamic power consumption.

Abstract translation: 在一个实施例中，多核处理器包括多个核和一个非核，其中该无孔包括包含高速缓冲存储器，路由器和功率控制单元（PCU）的各种逻辑单元。 当多核处理器处于低功率状态时，PCU可以对逻辑单元和高速缓冲存储器中的至少一个进行时钟门控，从而降低动态功耗。

公开(公告)号：WO2012005938A3

公开(公告)日：2012-01-12

申请号：PCT/US2011/041228

申请日：2011-06-21

Applicant: INTEL CORPORATION ,  RANGARAJAN, Thanunathan ,  GANESAN, Baskaran ,  BHATTACHARAYYA, Binata

Inventor： RANGARAJAN, Thanunathan ,  GANESAN, Baskaran ,  BHATTACHARAYYA, Binata

IPC: G06F11/07 ,  G06F12/08 ,  G06F9/46

Abstract: A semiconductor chip is described having different instances of cache agent logic circuitry for respective cache slices of a distributed cache. The semiconductor chip further includes hash engine logic circuitry comprising: hash logic circuitry to determine, based on an address, that a particular one of the cache slices is to receive a request having the address, and, a first input to receive notice of a failure event for the particular cache slice. The semiconductor chip also includes first circuitry to assign the address to another cache slice of the cache slices in response to the notice.

公开(公告)号：WO2013003159A2

公开(公告)日：2013-01-03

申请号：PCT/US2012043407

申请日：2012-06-20

Applicant: INTEL CORP ,  BURNS JAMES S ,  GANESAN BASKARAN ,  FENGER RUSSELL J ,  BODAS DEVADATTA V ,  IYENGAR SUNDARAVARATHAN R ,  NELSON FERANAK ,  POWELL JOHN M JR ,  SUGUMAR SURESH

Inventor： BURNS JAMES S ,  GANESAN BASKARAN ,  FENGER RUSSELL J ,  BODAS DEVADATTA V ,  IYENGAR SUNDARAVARATHAN R ,  NELSON FERANAK ,  POWELL JOHN M JR ,  SUGUMAR SURESH

CPC classification number: G06F1/3287 ,  G06F1/26 ,  G06F1/329 ,  G06F9/5094 ,  Y02D10/22 ,  Y02D10/24

Abstract: In one embodiment, a processor has multiple cores to execute threads. The processor further includes a power control logic to enable entry into a turbo mode based on a comparison between a threshold and value of a counter that stores a count of core power and performance combinations that identify turbo mode requests of at least one of the threads. In this way, turbo mode may be entered at a utilization level of the processor that provides for high power efficiency. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，处理器具有多个核以执行线程。 处理器还包括功率控制逻辑，用于基于存储核心功率的计数的计数器的阈值和值与识别至少一个线程的turbo模式请求的性能组合之间的比较，使得能够进入turbo模式。 以这种方式，可以在提供高功率效率的处理器的利用水平下输入涡轮模式。 描述并要求保护其他实施例。

公开(公告)号：WO2011025626A9

公开(公告)日：2011-05-26

申请号：PCT/US2010044089

申请日：2010-08-02

Applicant: INTEL CORP ,  NATU MAHESH S ,  GANESAN BASKARAN ,  RANGARAJAN THANUNATHAN ,  KUMAR MOHAN J ,  DOSHI GAUTAM B ,  PARTHASARATHY RAJESH S ,  DATTA SHAMMANNA M ,  BINNS FRANK ,  MURTHY RAJESH NAGARAJA ,  SWANSON ROBERT C

Inventor： NATU MAHESH S ,  GANESAN BASKARAN ,  RANGARAJAN THANUNATHAN ,  KUMAR MOHAN J ,  DOSHI GAUTAM B ,  PARTHASARATHY RAJESH S ,  DATTA SHAMMANNA M ,  BINNS FRANK ,  MURTHY RAJESH NAGARAJA ,  SWANSON ROBERT C

IPC: G06F13/10

CPC classification number: G06F13/24 ,  G06F9/30101 ,  G06F9/3017 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/461 ,  G11C7/1072 ,  G11C11/40615

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括处理器，该处理器具有诸如静态随机存取存储器的片上存储器，以存储在进入系统时被交换出处理器的架构状态存储器的一个或多个线程的架构状态 管理模式（SMM）。 通过这种方式，可以避免将此状态信息传送到系统管理存储器，从而减少与进入SMM相关的等待时间。 实施例还可以使得处理器能够更新处于长指令流程或处于系统管理中断（SMI）阻塞状态的执行代理的状态，以便向SMM内的代理提供指示。 描述并要求保护其他实施例。

公开(公告)号：WO2011025626A3

公开(公告)日：2011-03-03

申请号：PCT/US2010/044089

申请日：2010-08-02

Applicant: INTEL CORPORATION ,  NATU, Mahesh, S. ,  GANESAN, Baskaran ,  RANGARAJAN, Thanunathan ,  KUMAR, Mohan, J. ,  DOSHI, Gautam, B. ,  PARTHASARATHY, Rajesh, S. ,  DATTA, Shammanna, M. ,  BINNS, Frank ,  MURTHY, Rajesh Nagaraja ,  SWANSON, Robert, C.

Inventor： NATU, Mahesh, S. ,  GANESAN, Baskaran ,  RANGARAJAN, Thanunathan ,  KUMAR, Mohan, J. ,  DOSHI, Gautam, B. ,  PARTHASARATHY, Rajesh, S. ,  DATTA, Shammanna, M. ,  BINNS, Frank ,  MURTHY, Rajesh Nagaraja ,  SWANSON, Robert, C.

IPC: G06F13/10

Abstract: In one embodiment, the present invention includes a processor that has an on-die storage such as a static random access memory to store an architectural state of one or more threads that are swapped out of architectural state storage of the processor on entry to a system management mode (SMM). In this way communication of this state information to a system management memory can be avoided, reducing latency associated with entry into SMM. Embodiments may also enable the processor to update a status of executing agents that are either in a long instruction flow or in a system management interrupt (SMI) blocked state, in order to provide an indication to agents inside the SMM. Other embodiments are described and claimed.