公开(公告)号：WO2008061105A2

公开(公告)日：2008-05-22

申请号：PCT/US2007/084587

申请日：2007-11-13

Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  ANDERSON, William, C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis, Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

Inventor： CODRESCU, Lucian ,  ANDERSON, William, C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis, Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

IPC: G06F11/36

CPC classification number: G06F11/362 ,  G06F11/3656

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Stuffing instructions in a processing pipeline of a multi-threaded digital signal processor provides for operating a core processor process and a debugging process within a debugging mechanism. Writing a stuff instruction into a debugging process registry and a stuff command in a debugging process command register provides for identifying a predetermined thread of the multi-threaded digital signal processor in which to execute the stuff instruction. The instruction stuffing process issues a debugging process control resume command during a predetermined stage of executing on the predetermined thread and directs the core processor to perform the stuff instruction during the debugging process. The core processor may then execute the stuffed instruction in association with the core processor process and the debugging process.

Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 在多线程数字信号处理器的处理流水线中的填充指令提供了在调试机制内操作核心处理器进程和调试过程。 将填充指令写入调试进程注册表，并且调试进程命令寄存器中的填充命令用于标识执行填充指令的多线程数字信号处理器的预定线程。 指令填充处理在预定线程的预定执行阶段发出调试过程控制恢复命令，并指示核心处理器在调试过程中执行填充指令。 核心处理器然后可以与核心处理器进程和调试过程相关联地执行填充指令。

公开(公告)号：WO2008061067A2

公开(公告)日：2008-05-22

申请号：PCT/US2007/084456

申请日：2007-11-12

Applicant: QUALCOMM Incorporated ,  CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

Inventor： CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

CPC classification number: G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F11/362

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system provide for processing instructions in a multi-threaded process including the use of breakpoint instructions for generating debugging event(s). Generating a debugging event occurs in response to the execution of breakpoint instructions and executes debugging instructions in response to the debugging event. The debugging instructions debug processing instructions in the multi-threaded processor by transitioning at least one or more threads into a debugging mode. The disclosure generates a debugging return for reporting the executing debugging instructions in the subset of the threads of the multi-threaded processor.

Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 所公开的方法和系统提供处理多线程过程中的指令，包括使用断点指令来产生调试事件。 生成调试事件是为了响应断点指令的执行并执行调试指令来响应调试事件。 调试指令通过将至少一个或多个线程转换到调试模式来调试多线程处理器中的处理指令。 本公开生成用于报告多线程处理器的线程的子集中执行的调试指令的调试返回。

公开(公告)号：WO2008061086A3

公开(公告)日：2009-09-24

申请号：PCT/US2007084523

申请日：2007-11-13

Applicant: QUALCOMM INC ,  CODRESCU LUCIAN ,  ANDERSON WILLIAM C ,  VENKUMAHANTI SURESH ,  GIANNINI LOUIS ACHILLE ,  PYLA MANOJKUMAR ,  CHEN XUFENG

Inventor： CODRESCU LUCIAN ,  ANDERSON WILLIAM C ,  VENKUMAHANTI SURESH ,  GIANNINI LOUIS ACHILLE ,  PYLA MANOJKUMAR ,  CHEN XUFENG

IPC: G06F1/32 ,  G06F11/36

CPC classification number: G06F1/3203 ,  G06F11/362 ,  G06F11/3656

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. A method and system control transferring data between debugging registers and digital signal processor processes in association with a power transition sequence of the digital signal processor. In a digital signal processor, debugging registers associate with the core processor process and the debugging process. Control bits control transferring data among the debugging registers, the core processor process and the debugging process. The control bit prevents transferring data among the debugging registers, the core processor process and the debugging process in the event of a power transition sequence. Control bits also prevent a power transition sequence of the digital signal processor in the event of transferring data among the debugging registers and the core processor process or the debugging process.

Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 一种与数字信号处理器的功率转换序列相关联的在调试寄存器和数字信号处理器处理之间传送数据的方法和系统控制。 在数字信号处理器中，调试寄存器与核心处理器进程和调试过程相关联。 控制位控制在调试寄存器，核心处理器进程和调试过程之间传输数据。 控制位防止在电源转换序列的情况下在调试寄存器，核心处理器进程和调试过程之间传输数据。 在调试寄存器和核心处理器处理或调试过程之间传送数据的情况下，控制位还可以防止数字信号处理器的电源转换序列。

公开(公告)号：WO2008061067A3

公开(公告)日：2008-07-24

申请号：PCT/US2007084456

申请日：2007-11-12

Applicant: QUALCOMM INC ,  CODRESCU LUCIAN ,  ANDERSON WILLIAM C ,  VENKUMAHANTI SURESH ,  GIANNINI LOUIS ACHILLE ,  PYLA MANOJKUMAR ,  CHEN XUFENG

Inventor： CODRESCU LUCIAN ,  ANDERSON WILLIAM C ,  VENKUMAHANTI SURESH ,  GIANNINI LOUIS ACHILLE ,  PYLA MANOJKUMAR ,  CHEN XUFENG

IPC: G06F11/36

CPC classification number: G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F11/362

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system provide for processing instructions in a multi-threaded process including the use of breakpoint instructions for generating debugging event(s). Generating a debugging event occurs in response to the execution of breakpoint instructions and executes debugging instructions in response to the debugging event. The debugging instructions debug processing instructions in the multi-threaded processor by transitioning at least one or more threads into a debugging mode. The disclosure generates a debugging return for reporting the executing debugging instructions in the subset of the threads of the multi-threaded processor.

Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如CDMA）系统中的传输。 所公开的方法和系统提供了在多线程过程中处理指令，包括使用断点指令来产生调试事件。 响应于断点指令的执行而产生调试事件，并根据调试事件执行调试指令。 调试指令通过将至少一个或多个线程转变为调试模式来调试多线程处理器中的处理指令。 本公开生成用于报告多线程处理器的线程的子集中的执行调试指令的调试返回。

公开(公告)号：WO2008061102A3

公开(公告)日：2008-11-20

申请号：PCT/US2007084578

申请日：2007-11-13

Applicant: QUALCOMM INC ,  CODRESCU LUCIAN ,  ANDERSON WILLIAM C ,  VENKUMAHANTI SURESH ,  GIANNINI LOUIS ACHILLE ,  PYLA MANOJKUMAR ,  CHEN XUFENG

Inventor： CODRESCU LUCIAN ,  ANDERSON WILLIAM C ,  VENKUMAHANTI SURESH ,  GIANNINI LOUIS ACHILLE ,  PYLA MANOJKUMAR ,  CHEN XUFENG

IPC: G06F11/36

CPC classification number: G06F11/3656 ,  G06F9/3005

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The method and system improve software instruction debugging operations by capturing real-time information relating to software execution flow and include and instructions and circuitry for operating a core processor process within a core processor. A non-intrusive debugging process operates within a debugging mechanism of a digital signal processor. Non-intrusively monitoring in real time predetermined aspects of software execution occurs with the core processing process and occurs in real-time on the processor. An embedded trace macrocell records selectable aspects of the non-intrusively monitored software execution and generates at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution. The present disclosure controls aspects of the non-intrusive debugging process in response to at least one breakpoint.

Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 该方法和系统通过捕获与软件执行流程相关的实时信息来改进软件指令调试操作，并且包括用于在核心处理器内操作核心处理器进程的指令和电路。 非侵入式调试过程在数字信号处理器的调试机制中运行。 非实时监控软件执行的预定方面与核心处理过程相关，并在处理器上实时发生。 嵌入式跟踪宏单元记录非侵入式监视的软件执行的可选方面，并且响应于在非侵入式监视的软件执行的可选择方面内产生的事件而生成至少一个断点。 本公开内容响应于至少一个断点来控制非侵入式调试过程的方面。

公开(公告)号：WO2008061105A3

公开(公告)日：2008-11-06

申请号：PCT/US2007084587

申请日：2007-11-13

Applicant: QUALCOMM INC ,  CODRESCU LUCIAN ,  ANDERSON WILLIAM C ,  VENKUMAHANTI SURESH ,  GIANNINI LOUIS ACHILLE ,  PYLA MANOJKUMAR ,  CHEN XUFENG

Inventor： CODRESCU LUCIAN ,  ANDERSON WILLIAM C ,  VENKUMAHANTI SURESH ,  GIANNINI LOUIS ACHILLE ,  PYLA MANOJKUMAR ,  CHEN XUFENG

IPC: G06F11/36

CPC classification number: G06F11/362 ,  G06F11/3656

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Stuffing instructions in a processing pipeline of a multi-threaded digital signal processor provides for operating a core processor process and a debugging process within a debugging mechanism. Writing a stuff instruction into a debugging process registry and a stuff command in a debugging process command register provides for identifying a predetermined thread of the multi-threaded digital signal processor in which to execute the stuff instruction. The instruction stuffing process issues a debugging process control resume command during a predetermined stage of executing on the predetermined thread and directs the core processor to perform the stuff instruction during the debugging process. The core processor may then execute the stuffed instruction in association with the core processor process and the debugging process.

Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）处理通信（例如，CDMA）系统中的传输。 在多线程数字信号处理器的处理流水线中填充指令提供了在调试机制内操作核心处理器进程和调试进程。 在调试进程注册表中写入填充指令并且在调试进程命令寄存器中填充填充命令用于标识要在其中执行填充指令的多线程数字信号处理器的预定线程。 指令填充过程在预定线程上执行的预定阶段期间发出调试过程控制恢复命令，并指示核心处理器在调试过程期间执行填充指令。 核心处理器然后可以执行与核心处理器进程和调试进程相关联的填充指令。

公开(公告)号：WO2008128107A3

公开(公告)日：2008-10-23

申请号：PCT/US2008/060117

申请日：2008-04-11

Applicant: QUALCOMM Incorporated ,  GIANNINI, Louis Achille ,  ANDERSON, William C. ,  CHEN, Xufeng

Inventor： GIANNINI, Louis Achille ,  ANDERSON, William C. ,  CHEN, Xufeng

IPC: G06F11/36

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Inter-thread trace alignment with execution trace processing includes recording timing data relating to a common predetermined event. Such an event may be the number of cycles since a last thread initiated execution tracing or the number of cycles since all threads terminated execution tracing. The number of cycles at which a thread initiates execution tracing is referenced to the common predetermined event for maintaining the timing of execution tracing. The data relating to the common predetermined event is then updated to associate with the time at which the thread initiated execution tracing. The result is to permit aligning the timing data associated with all threads. Interrelated records permit reconstructing interdependent execution tracing information for threads operating in the multi-threaded processor, as well as synchronizing timing data for all operating threads.

公开(公告)号：WO2008061089A3

公开(公告)日：2008-05-22

申请号：PCT/US2007/084530

申请日：2007-11-13

Applicant: QUALCOMM Incorporated ,  CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

Inventor： CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

IPC: G06F11/36

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Trusted and untrusted debugging operational control occurs in operating a core processor associated with the digital signal processor. A debugging process within a debugging mechanism associates with the core processor. The core processor process determines the origin of debugging control as trusted debugging control or untrusted debugging control. In the event of trusted debugging control, the core processor process provides to the trusted debugging control a first set of features and privileges. Alternatively, in the event that debugging control is untrusted debugging control, the core processor process provides the untrusted debugging control a second restricted set of features and privileges, all for maintaining security and proper operation of the core processor process.

公开(公告)号：WO2008061089A2

公开(公告)日：2008-05-22

申请号：PCT/US2007084530

申请日：2007-11-13

Applicant: QUALCOMM INC ,  CODRESCU LUCIAN ,  ANDERSON WILLIAM C ,  VENKUMAHANTI SURESH ,  GIANNINI LOUIS ACHILLE ,  PYLA MANOJKUMAR ,  CHEN XUFENG

Inventor： CODRESCU LUCIAN ,  ANDERSON WILLIAM C ,  VENKUMAHANTI SURESH ,  GIANNINI LOUIS ACHILLE ,  PYLA MANOJKUMAR ,  CHEN XUFENG

IPC: G06F11/36

CPC classification number: G06F11/3656

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Trusted and untrusted debugging operational control occurs in operating a core processor associated with the digital signal processor. A debugging process within a debugging mechanism associates with the core processor. The core processor process determines the origin of debugging control as trusted debugging control or untrusted debugging control. In the event of trusted debugging control, the core processor process provides to the trusted debugging control a first set of features and privileges. Alternatively, in the event that debugging control is untrusted debugging control, the core processor process provides the untrusted debugging control a second restricted set of features and privileges, all for maintaining security and proper operation of the core processor process.

Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）处理通信（例如，CDMA）系统中的传输。 在操作与数字信号处理器相关的核心处理器时发生可信和不可信的调试操作控制。 调试机制内的调试过程与核心处理器相关联。 核心处理器进程将调试控制的来源确定为可信调试控制或不可信调试控制。 在可信调试控制的情况下，核心处理器进程向可信调试控制器提供第一组特征和特权。 或者，如果调试控制是不可信的调试控制，则核心处理器进程向不可信的调试控制提供第二组有限的功能和特权，这些都用于维护核心处理器进程的安全性和正确操作。

公开(公告)号：WO2010135428A2

公开(公告)日：2010-11-25

申请号：PCT/US2010/035406

申请日：2010-05-19

Applicant: QUALCOMM INCORPORATED ,  VENKUMAHANTI, Suresh K. ,  CHAN, Robert Shuicheong ,  BALASUNDARAM, Prasanna Kumar ,  GIANNINI, Louis Achille

Inventor： VENKUMAHANTI, Suresh K. ,  CHAN, Robert Shuicheong ,  BALASUNDARAM, Prasanna Kumar ,  GIANNINI, Louis Achille

IPC: G06F1/32 ,  G06F9/06 ,  G06F1/04 ,  G06F13/14

CPC classification number: G06F11/3632

Abstract: Methods, apparatuses, and computer-readable storage media are disclosed for reducing power by reducing hardware-thread toggling in a multi-processor. In a particular embodiment, a method is disclosed that includes collecting data from a plurality of software threads being processed by a processor, where the data for each of the events includes a value of an associated clock cycle counter upon occurrence of the event. Data is correlated for the events occurring for each of the plurality of threads by starting each of a plurality of clock cycle counters associated with the software threads at a common time. Alternatively, data is correlated for the events by logging a synchronizing event within each of the plurality of software threads.

Abstract translation: 公开了用于通过减少多处理器中的硬件线程切换来降低功率的方法，装置和计算机可读存储介质。 在特定实施例中，公开了一种方法，其包括从由处理器处理的多个软件线程收集数据，其中每个事件的数据在事件发生时包括相关联的时钟周期计数器的值。 通过在公共时间启动与软件线程相关联的多个时钟周期计数器中的每一个，数据与针对多个线程中的每一个发生的事件相关。 或者，通过在多个软件线程的每一个内记录同步事件来将数据与事件相关联。