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    THREAD ALLOCATION AND CLOCK CYCLE ADJUSTMENT IN AN INTERLEAVED MULTI-THREADED PROCESSOR
    1.
    发明申请
    THREAD ALLOCATION AND CLOCK CYCLE ADJUSTMENT IN AN INTERLEAVED MULTI-THREADED PROCESSOR 审中-公开
    交叉多线程处理器中的螺纹分配和时钟周期调整

    公开(公告)号：WO2011072083A1

    公开(公告)日：2011-06-16

    申请号：PCT/US2010/059579

    申请日：2010-12-08

    Applicant: QUALCOMM INCORPORATED ,  VENKUMAHANTI, Suresh, K. ,  SAINT-LAURENT, Martin ,  CODRESCU, Lucian ,  MOHAMMAD, Baker, S.

    Inventor： VENKUMAHANTI, Suresh, K. ,  SAINT-LAURENT, Martin ,  CODRESCU, Lucian ,  MOHAMMAD, Baker, S.

    IPC: G06F9/38 ,  G06F9/50

    CPC classification number: G01R1/07378 ,  G01R3/00 ,  G01R31/2846 ,  G01R31/2889 ,  G01R31/2896 ,  G06F9/3851

    Abstract: Methods, apparatuses, and computer-readable storage media are disclosed for reducing power by reducing hardware-thread toggling in a multi-threaded processor. In a particular embodiment, a method allocates software threads to hardware threads. A number of software threads to be allocated is identified. It is determined when the number of software threads is less than a number of hardware threads. When the number of software threads is less than the number of hardware threads, at least two of the software threads are allocated to non-sequential hardware threads. A clock signal to be applied to the hardware threads is adjusted responsive to the non-sequential hardware threads allocated.

    Abstract translation: 公开了用于通过减少多线程处理器中的硬件线程切换来降低功率的方法，装置和计算机可读存储介质。 在特定实施例中，一种方法将软件线程分配给硬件线程。 识别要分配的多个软件线程。 何时软件线程的数量少于多个硬件线程。 当软件线程的数量小于硬件线程数时，至少两个软件线程被分配给非顺序硬件线程。 响应于所分配的非顺序硬件线程调整应用于硬件线程的时钟信号。

    ASSOCIATING DATA FOR EVENTS OCCURRING IN SOFTWARE THREADS WITH SYNCHRONIZED CLOCK CYCLE COUNTERS
    2.
    发明申请
    ASSOCIATING DATA FOR EVENTS OCCURRING IN SOFTWARE THREADS WITH SYNCHRONIZED CLOCK CYCLE COUNTERS 审中-公开
    与同步时钟周期计数器相关的软件线程事件相关数据

    公开(公告)号：WO2010135428A2

    公开(公告)日：2010-11-25

    申请号：PCT/US2010/035406

    申请日：2010-05-19

    Applicant: QUALCOMM INCORPORATED ,  VENKUMAHANTI, Suresh K. ,  CHAN, Robert Shuicheong ,  BALASUNDARAM, Prasanna Kumar ,  GIANNINI, Louis Achille

    Inventor： VENKUMAHANTI, Suresh K. ,  CHAN, Robert Shuicheong ,  BALASUNDARAM, Prasanna Kumar ,  GIANNINI, Louis Achille

    IPC: G06F1/32 ,  G06F9/06 ,  G06F1/04 ,  G06F13/14

    CPC classification number: G06F11/3632

    Abstract: Methods, apparatuses, and computer-readable storage media are disclosed for reducing power by reducing hardware-thread toggling in a multi-processor. In a particular embodiment, a method is disclosed that includes collecting data from a plurality of software threads being processed by a processor, where the data for each of the events includes a value of an associated clock cycle counter upon occurrence of the event. Data is correlated for the events occurring for each of the plurality of threads by starting each of a plurality of clock cycle counters associated with the software threads at a common time. Alternatively, data is correlated for the events by logging a synchronizing event within each of the plurality of software threads.

    Abstract translation: 公开了用于通过减少多处理器中的硬件线程切换来降低功率的方法，装置和计算机可读存储介质。 在特定实施例中，公开了一种方法，其包括从由处理器处理的多个软件线程收集数据，其中每个事件的数据在事件发生时包括相关联的时钟周期计数器的值。 通过在公共时间启动与软件线程相关联的多个时钟周期计数器中的每一个，数据与针对多个线程中的每一个发生的事件相关。 或者，通过在多个软件线程的每一个内记录同步事件来将数据与事件相关联。

    EMBEDDED TRACE MACROCELL FOR ENHANCED DIGITAL SIGNAL PROCESSOR DEBUGGING OPERATIONS
    4.
    发明申请
    EMBEDDED TRACE MACROCELL FOR ENHANCED DIGITAL SIGNAL PROCESSOR DEBUGGING OPERATIONS 审中-公开
    用于增强型数字信号处理器调试操作的嵌入式宏跟踪器

    公开(公告)号：WO2008061102A2

    公开(公告)日：2008-05-22

    申请号：PCT/US2007/084578

    申请日：2007-11-13

    Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

    Inventor： CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

    IPC: G06F11/36

    CPC classification number: G06F11/3656 ,  G06F9/3005

    Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The method and system improve software instruction debugging operations by capturing real-time information relating to software execution flow and include and instructions and circuitry for operating a core processor process within a core processor. A non-intrusive debugging process operates within a debugging mechanism of a digital signal processor. Non-intrusively monitoring in real time predetermined aspects of software execution occurs with the core processing process and occurs in real-time on the processor. An embedded trace macrocell records selectable aspects of the non-intrusively monitored software execution and generates at least one breakpoint in response to events arising within the selectable aspects of the non-intrusively monitored software execution. The present disclosure controls aspects of the non-intrusive debugging process in response to at least one breakpoint.

    Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 该方法和系统通过捕获与软件执行流有关的实时信息来改进软件指令调试操作，并且包括用于在核心处理器内操作核心处理器过程的指令和电路。 非侵入式调试过程在数字信号处理器的调试机制内运行。 实时非侵入式地监控软件执行的预定方面与核心处理过程一起发生并且在处理器上实时发生。 嵌入式跟踪宏小区记录非侵入式监控的软件执行的可选方面并且响应于在非侵入式监控的软件执行的可选方面内出现的事件而产生至少一个断点。 本公开内容响应于至少一个断点来控制非侵入式调试过程的各个方面。

    LOOP CONTROL SYSTEM AND METHOD
    6.
    发明申请
    LOOP CONTROL SYSTEM AND METHOD 审中-公开
    环路控制系统和方法

    公开(公告)号：WO2009158370A3

    公开(公告)日：2010-02-25

    申请号：PCT/US2009048370

    申请日：2009-06-24

    Applicant: QUALCOMM INC ,  CODRESCU LUCIAN ,  PLONDKE ERICH ,  WANG LIN ,  VENKUMAHANTI SURESH K

    Inventor： CODRESCU LUCIAN ,  PLONDKE ERICH ,  WANG LIN ,  VENKUMAHANTI SURESH K

    IPC: G06F9/445

    CPC classification number: G06F8/4452 ,  G06F9/30072 ,  G06F9/325 ,  G06F9/3853 ,  G06F9/3885

    Abstract: Loop control systems and methods are disclosed. In a particular embodiment, a hardware loop control logic circuit includes a detection unit to detect an end of loop indicator of a program loop. The hardware loop control logic circuit also includes a decrement unit to decrement a loop count and to decrement a predicate trigger counter. The hardware loop control logic circuit further includes a comparison unit to compare the predicate trigger counter to a reference to determine when to set a predicate value.

    Abstract translation: 公开了回路控制系统和方法。 在特定实施例中，硬件回路控制逻辑电路包括检测单元以检测程序循环的循环指示符的结束。 硬件回路控制逻辑电路还包括递减单元，用于递减循环计数并递减谓词触发计数器。 硬件循环控制逻辑电路还包括比较单元，用于将谓词触发计数器与参考值进行比较，以确定何时设置谓词值。

    METHOD AND SYSTEM FOR INSTRUCTION STUFFING OPERATIONS DURING NON-INTRUSIVE DIGITAL SIGNAL PROCESSOR DEBUGGING
    8.
    发明申请
    METHOD AND SYSTEM FOR INSTRUCTION STUFFING OPERATIONS DURING NON-INTRUSIVE DIGITAL SIGNAL PROCESSOR DEBUGGING 审中-公开
    非侵入式数字信号处理器调试期间的指令运行操作方法与系统

    公开(公告)号：WO2008061105A2

    公开(公告)日：2008-05-22

    申请号：PCT/US2007/084587

    申请日：2007-11-13

    Applicant: QUALCOMM INCORPORATED ,  CODRESCU, Lucian ,  ANDERSON, William, C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis, Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

    Inventor： CODRESCU, Lucian ,  ANDERSON, William, C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis, Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

    IPC: G06F11/36

    CPC classification number: G06F11/362 ,  G06F11/3656

    Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. Stuffing instructions in a processing pipeline of a multi-threaded digital signal processor provides for operating a core processor process and a debugging process within a debugging mechanism. Writing a stuff instruction into a debugging process registry and a stuff command in a debugging process command register provides for identifying a predetermined thread of the multi-threaded digital signal processor in which to execute the stuff instruction. The instruction stuffing process issues a debugging process control resume command during a predetermined stage of executing on the predetermined thread and directs the core processor to perform the stuff instruction during the debugging process. The core processor may then execute the stuffed instruction in association with the core processor process and the debugging process.

    Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 在多线程数字信号处理器的处理流水线中的填充指令提供了在调试机制内操作核心处理器进程和调试过程。 将填充指令写入调试进程注册表，并且调试进程命令寄存器中的填充命令用于标识执行填充指令的多线程数字信号处理器的预定线程。 指令填充处理在预定线程的预定执行阶段发出调试过程控制恢复命令，并指示核心处理器在调试过程中执行填充指令。 核心处理器然后可以与核心处理器进程和调试过程相关联地执行填充指令。

    NON-INTRUSIVE, THREAD-SELECTIVE, DEBUGGING METHOD AND SYSTEM FOR A MULTI-THREADED DIGITAL SIGNAL PROCESSOR
    9.
    发明申请
    NON-INTRUSIVE, THREAD-SELECTIVE, DEBUGGING METHOD AND SYSTEM FOR A MULTI-THREADED DIGITAL SIGNAL PROCESSOR 审中-公开
    多线程数字信号处理器的非侵入性，线性选择，调试方法和系统

    公开(公告)号：WO2008061067A2

    公开(公告)日：2008-05-22

    申请号：PCT/US2007/084456

    申请日：2007-11-12

    Applicant: QUALCOMM Incorporated ,  CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

    Inventor： CODRESCU, Lucian ,  ANDERSON, William C. ,  VENKUMAHANTI, Suresh ,  GIANNINI, Louis Achille ,  PYLA, Manojkumar ,  CHEN, Xufeng

    CPC classification number: G06F9/3005 ,  G06F9/3009 ,  G06F9/3851 ,  G06F11/362

    Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) for processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system provide for processing instructions in a multi-threaded process including the use of breakpoint instructions for generating debugging event(s). Generating a debugging event occurs in response to the execution of breakpoint instructions and executes debugging instructions in response to the debugging event. The debugging instructions debug processing instructions in the multi-threaded processor by transitioning at least one or more threads into a debugging mode. The disclosure generates a debugging return for reporting the executing debugging instructions in the subset of the threads of the multi-threaded processor.

    Abstract translation: 用于设计和使用数字信号处理器的技术，包括（但不限于）用于处理通信（例如，CDMA）系统中的传输。 所公开的方法和系统提供处理多线程过程中的指令，包括使用断点指令来产生调试事件。 生成调试事件是为了响应断点指令的执行并执行调试指令来响应调试事件。 调试指令通过将至少一个或多个线程转换到调试模式来调试多线程处理器中的处理指令。 本公开生成用于报告多线程处理器的线程的子集中执行的调试指令的调试返回。

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