公开(公告)号：WO2013006231A3

公开(公告)日：2013-04-04

申请号：PCT/US2012039268

申请日：2012-05-24

Applicant: RAMBUS INC ,  ZERBE JARED L ,  LEIBOWITZ BRIAN S ,  HOSSAIN MASUM

Inventor： ZERBE JARED L ,  LEIBOWITZ BRIAN S ,  HOSSAIN MASUM

IPC: H03K5/00 ,  H03B19/00

CPC classification number: H03L7/16 ,  H03J2200/10 ,  H03K3/0315 ,  H03K5/00006 ,  H03K5/13 ,  H03K5/14 ,  H03L7/06 ,  H03L7/0995 ,  H03L7/24

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally- staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

Abstract translation: 在第一时钟倍频器中，并行操作具有光谱交错锁定范围的多个注入锁定振荡器（ILO），以实现比单独ILO的集中输入频率范围宽得多的集中输入频率范围。 在每个输入频率改变之后，可以根据一个或多个合格标准评估ILO输出时钟，以选择ILO中的一个作为最终时钟源。 在第二个时钟倍频器中，柔性注入速率注入锁定振荡器锁定超级谐波，次谐波或频率注入脉冲，在不同的注入脉冲速率之间无缝切换，以实现宽泛的输入频率范围。 由第一和/或第二时钟倍频器响应于输入时钟而实现的倍频因子被实时确定，然后与编程的（期望的）倍增因子进行比较以在倍频的不同分频实例之间进行选择 时钟。

公开(公告)号：WO2013006231A2

公开(公告)日：2013-01-10

申请号：PCT/US2012/039268

申请日：2012-05-24

Applicant: RAMBUS INC. ,  ZERBE, Jared, L. ,  LEIBOWITZ, Brian, S. ,  HOSSAIN, Masum

Inventor： ZERBE, Jared, L. ,  LEIBOWITZ, Brian, S. ,  HOSSAIN, Masum

CPC classification number: H03L7/16 ,  H03J2200/10 ,  H03K3/0315 ,  H03K5/00006 ,  H03K5/13 ,  H03K5/14 ,  H03L7/06 ,  H03L7/0995 ,  H03L7/24

Abstract: In a first clock frequency multiplier, multiple injection-locked oscillators (ILOs) having spectrally- staggered lock ranges are operated in parallel to effect a collective input frequency range substantially wider than that of a solitary ILO. After each input frequency change, the ILO output clocks may be evaluated according to one or more qualifying criteria to select one of the ILOs as the final clock source. In a second clock frequency multiplier, a flexible-injection-rate injection-locked oscillator locks to super-harmonic, sub-harmonic or at-frequency injection pulses, seamlessly transitioning between the different injection pulse rates to enable a broad input frequency range. The frequency multiplication factor effected by the first and/or second clock frequency multipliers in response to an input clock is determined on the fly and then compared with a programmed (desired) multiplication factor to select between different frequency-divided instances of the frequency-multiplied clock.

Abstract translation: 在第一时钟频率乘法器中，具有光谱交错锁定范围的多个注入锁定振荡器（ILO）并行操作，以实现比单独国际劳工组织宽的集体输入频率范围。 在每个输入频率变化之后，可以根据一个或多个限定条件评估国际劳工组织输出时钟，以选择其中一个ILO作为最终的时钟源。 在第二个时钟倍频器中，灵活注入速率的注入锁定振荡器锁定到超谐波，次谐波或全频率注入脉冲，在不同的注入脉冲速率之间无缝转换，以实现宽的输入频率范围。 响应于输入时钟由第一和/或第二时钟频率乘法器影响的倍频因子在飞行中确定，然后与编程的（期望的）乘法因子进行比较，以在频率乘法器的不同分频实例之间进行选择 时钟。

公开(公告)号：WO2013137863A1

公开(公告)日：2013-09-19

申请号：PCT/US2012/028912

申请日：2012-03-13

Applicant: RAMBUS INC. ,  HOSSAIN, Masum ,  LEIBOWITZ, Brian ,  REN, Jihong

Inventor： HOSSAIN, Masum ,  LEIBOWITZ, Brian ,  REN, Jihong

IPC: H03L7/085 ,  H04L7/033

CPC classification number: H04L7/0016 ,  H03L7/1974 ,  H03L7/235 ,  H04L7/033 ,  H04L27/0014 ,  H04L27/32 ,  H04L2027/0016 ,  H04L2027/0036 ,  H04L2027/0053 ,  H04L2027/0055 ,  H04L2027/0067

Abstract: This disclosure provides a clock recovery circuit for a multi-lane communication system. Local clocks are recovered from the input signals using respective local CDR circuits, and associated CDR error signals are aggregated or otherwise combined. A global recovered clock for shared use by the local CDR circuits is generated at a controllable oscillation frequency as a function of a combination of the error signals from the plurality of receivers. A voltage- or current- controlled delay line can also be used to phase adjust the global recovered clock to mitigate band-limited, lane-correlated, high frequency jitter.

Abstract translation: 本公开提供了一种用于多车道通信系统的时钟恢复电路。 使用相应的本地CDR电路从输入信号恢复本地时钟，并且相关联的CDR错误信号被聚合或以其他方式组合。 作为来自多个接收机的误差信号的组合的函数的可控振荡频率产生由本地CDR电路共享使用的全局恢复时钟。 电压或电流控制延迟线也可用于相位调整全局恢复时钟，以减轻带限制，通道相关的高频抖动。