公开(公告)号：WO2014143056A1

公开(公告)日：2014-09-18

申请号：PCT/US2013/032633

申请日：2013-03-15

Applicant: INTEL CORPORATION ,  NALE, Bill ,  JASPER, Jonathan C. ,  LOVELACE, John V. ,  NACHIMUTHU, Murugasamy K. ,  ZHU, Jun ,  QUACH, Tuan M.

Inventor： NALE, Bill ,  JASPER, Jonathan C. ,  LOVELACE, John V. ,  NACHIMUTHU, Murugasamy K. ,  ZHU, Jun ,  QUACH, Tuan M.

IPC: G11C7/10 ,  G11C7/22 ,  G06F13/14

CPC classification number: G06F11/0793 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0629 ,  G06F3/0638 ,  G06F3/0673 ,  G06F3/0683 ,  G06F11/0727 ,  G06F11/0751 ,  G06F11/0772 ,  G06F11/079 ,  G06F12/023 ,  G06F12/0802 ,  G06F12/0813 ,  G06F13/1663 ,  G06F13/1678 ,  G06F13/1689 ,  G06F13/1694 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G06F2212/1044 ,  G06F2212/2532 ,  G06F2212/60 ,  G11C5/04 ,  G11C5/148 ,  G11C7/1003 ,  G11C7/1063 ,  G11C7/1072 ,  G11C7/222 ,  G11C11/40618 ,  G11C29/023 ,  G11C29/028 ,  H04L9/0869

Abstract: Provided is a device for use in a memory module coupled to a host memory controller over a bus, comprising memory module control logic to generate a request signal to a host memory controller having a pulse width greater than or equal to a minimum pulse width, wherein the minimum pulse width comprises a number of clock cycles needed to guarantee that the host memory controller detects the request signal, and wherein the pulse width of the request signal indicates at least one function in addition to the request signal to the host memory controller.

Abstract translation: 提供了一种用于通过总线耦合到主机存储器控制器的存储器模块中的装置，包括存储器模块控制逻辑，以产生具有大于或等于最小脉冲宽度的脉冲宽度的主机存储器控制器的请求信号，其中 最小脉冲宽度包括保证主机存储器控制器检测到请求信号所需的多个时钟周期，并且其中请求信号的脉冲宽度除了向主机存储器控制器的请求信号之外还指示至少一个功能。

公开(公告)号：WO2011084224A2

公开(公告)日：2011-07-14

申请号：PCT/US2010055454

申请日：2010-11-04

Applicant: INTEL CORP ,  NATU MAHESH S ,  LOVELACE JOHN V ,  BANGINWAR RAJESH P

Inventor： NATU MAHESH S ,  LOVELACE JOHN V ,  BANGINWAR RAJESH P

IPC: G06F13/14 ,  G06F9/44 ,  G06F13/38

CPC classification number: G06F21/74 ,  G06F9/4403 ,  G06F21/44 ,  G06F21/575 ,  G06F21/71 ,  G06F21/73 ,  G06F21/85 ,  G06F2221/2105 ,  G06F2221/2129 ,  G06F2221/2149 ,  G06F2221/2153

Abstract: Memory channel training parameters are function of electrical characteristics of memory devices, processor(s) and memory channel(s). Training steps can be skipped if the BIOS can determine that the memory devices, motherboard and processor have not changed since the last boot. Memory devices contain a serial number for tracking purposes and most motherboards contain a serial number. Many processors do not provide a mechanism by which the BIOS can track the processor. Described herein are techniques that allow the BIOS to track a processor and detect a swap without violating privacy/security requirements.

Abstract translation: 存储器通道训练参数是存储器设备，处理器和存储器通道的电气特性的函数。 如果BIOS可以确定自上次启动以来内存设备，主板和处理器未发生更改，则可跳过培训步骤。 内存设备包含用于追踪目的的序列号，大多数主板包含序列号。 许多处理器不提供BIOS可以跟踪处理器的机制。 这里描述的是允许BIOS跟踪处理器并检测交换而不违反隐私/安全要求的技术。

公开(公告)号：WO2011084224A3

公开(公告)日：2011-07-14

申请号：PCT/US2010/055454

申请日：2010-11-04

Applicant: INTEL CORPORATION ,  NATU, Mahesh, S. ,  LOVELACE, John, V. ,  BANGINWAR, Rajesh, P.

Inventor： NATU, Mahesh, S. ,  LOVELACE, John, V. ,  BANGINWAR, Rajesh, P.

IPC: G06F13/14 ,  G06F13/38 ,  G06F9/44

Abstract: Memory channel training parameters are function of electrical characteristics of memory devices, processor(s) and memory channel(s). Training steps can be skipped if the BIOS can determine that the memory devices, motherboard and processor have not changed since the last boot. Memory devices contain a serial number for tracking purposes and most motherboards contain a serial number. Many processors do not provide a mechanism by which the BIOS can track the processor. Described herein are techniques that allow the BIOS to track a processor and detect a swap without violating privacy/security requirements.