公开(公告)号：WO2008010908A3

公开(公告)日：2008-04-17

申请号：PCT/US2007015281

申请日：2007-07-09

Applicant: QUICKFILTER TECHNOLOGIES INC ,  LEONARD JERAMY ,  ELLIOTT WILLIAM ,  MAGDEBURGER THOMAS

Inventor： LEONARD JERAMY ,  ELLIOTT WILLIAM ,  MAGDEBURGER THOMAS

IPC: H03M1/12

CPC classification number: H03H17/0294 ,  H03H17/06

Abstract: An analog-to-digital conversion system has an analog-to-digital converter (300) and a digital-filter system (100). The digital-filter system (100) is connected to the output of the analog-to-digital converter (300). A processor (310) is connected to the output of the digital-filter system (100) so that the processor (310) transparently receives filtered sample data in the native format of the analog-to-digital converter (300). An FIR filter circuit (130) in the digital-filter system (100) is connected to receive data from, and output filtered data to, a sample capture and data-type conversion circuit (120) connected between the analog-to-digital converter (300) and the processor (310). A configuration and control-register circuit (110) is connected to the circuit for sample collection and data-type conversion (120), and to the FIR filter circuit (130), for selectively controlling the operation of the digital filter system (100) according to parameters for data conversion and filter operation passed to the configuration and control-register circuit (110) over a serial interface.

Abstract translation: 模拟 - 数字转换系统具有模数转换器（300）和数字滤波器系统（100）。 数字滤波器系统（100）连接到模拟 - 数字转换器（300）的输出端。 处理器（310）连接到数字滤波器系统（100）的输出，使得处理器（310）以模数转换器（300）的本机格式透明地接收滤波后的采样数据。 数字滤波器系统（100）中的FIR滤波器电路（130）被连接以从滤波数据接收数据，并将滤波后的数据输出到连接在模数转换器之间的采样捕获和数据类型转换电路（120） （300）和处理器（310）。 配置和控制寄存器电路（110）连接到用于采样和数据类型转换的电路（120）和FIR滤波器电路（130），用于选择性地控制数字滤波器系统（100）的操作， 根据用于通过串行接口传送到配置和控制寄存器电路（110）的数据转换和滤波操作的参数。

公开(公告)号：WO2007032895A3

公开(公告)日：2008-06-19

申请号：PCT/US2006033469

申请日：2006-08-29

Applicant: QUICKFILTER TECHNOLOGIES INC ,  MAGDEBURGER THOMAS ,  HEADLEY AARON

Inventor： MAGDEBURGER THOMAS ,  HEADLEY AARON

IPC: G06F7/00

CPC classification number: G06F13/385

Abstract: A serial interface controller (200) provides for transferring data between a data source having a least one channel (110) and a processor. The serial interface controller (200) has a plurality of control registers (220); the control registers (220) in turn include a data structure for configuring the serial interface controller (200) for a data transfer. That data structure further comprises a field for selectively setting the serial interface controller (200) in its run mode or its configuration mode; a field for storing the I/O mode of the serial interface controller (200); a field for storing the address of the active data channel; and, a field for storing the system clock rate. In the preferred embodiment, the control registers (220) include fields for device identification, a flag for the run or configure mode, a I/O-mode control, a value for the channels active (in multi-channel implementations), the data source clock rate, the ADC clock rate, channel-status flags, the CIC decimation rate, the number of taps for FIR filters, and the filter coefficients corresponding to the number of FIR taps in a particular data source.

Abstract translation: 串行接口控制器（200）提供用于在具有至少一个通道（110）的数据源和处理器之间传送数据。 串行接口控制器（200）具有多个控制寄存器（220）; 控制寄存器（220）又包括用于配置用于数据传送的串行接口控制器（200）的数据结构。 该数据结构还包括用于选择性地将串行接口控制器（200）设置为其运行模式或其配置模式的字段; 用于存储串行接口控制器（200）的I / O模式的字段; 用于存储活动数据信道的地址的字段; 以及用于存储系统时钟速率的字段。 在优选实施例中，控制寄存器（220）包括用于设备识别的字段，用于运行或配置模式的标志，I / O模式控制，用于通道活动的（多通道实现中）的值，数据 源时钟速率，ADC时钟速率，信道状态标志，CIC抽取率，FIR滤波器的抽头数，以及与特定数据源中FIR抽头数量相对应的滤波器系数。

公开(公告)号：WO2007027692A3

公开(公告)日：2008-09-18

申请号：PCT/US2006033725

申请日：2006-08-29

Applicant: QUICKFILTER TECHNOLOGIES INC ,  MAGDEBURGER THOMAS ,  BEST DENNIS

Inventor： MAGDEBURGER THOMAS ,  BEST DENNIS

IPC: G06F17/10

CPC classification number: G06F7/5443

Abstract: An integrated circuit for implementing a digital filter has a data memory (100); the data memory (100) having two ports (210, 220) to permit the access of two data samples at the same time, and a coefficient memory (105) for storing filter coefficients. A first adder (110) adds data samples from first and second data memory ports (210, 220); a multiplier (115) multiplies a value from the first adder (110) by a value from the coefficient memory (105); and, a second adder accumulates values from the multiplier (115). A master controller (190) is provided configured for selectively storing the accumulated values in the data memory (100) for further processing or outputting the accumulated values. An address and control block (125) communicating with the data memory (100) and the coefficient memory (105) holds values appropriate to the filter to be executed. The address and control block (125) has two sets of a first set of registers for holding values for a first pre-determined digital filter and a second pre-determined digital filter in cascade. The method maintains a current write address for data in the address and control block (125) as a circular list, where the circular list has a size equal to a predetermined number of filter taps;. The method maintains a first read address for data from the first port as a first-in-first-out queue, a second read address for data from the second port as a last-in-first-out stack, and a coefficient read address as a circular list.

Abstract translation: 一种用于实现数字滤波器的集成电路具有数据存储器（100）; 数据存储器（100）具有允许同时访问两个数据样本的两个端口（210,220）和用于存储滤波器系数的系数存储器（105）。 第一加法器（110）将来自第一和第二数据存储器端口（210,220）的数据样本相加; 乘法器（115）将来自第一加法器（110）的值与来自系数存储器（105）的值相乘; 并且第二加法器累加来自乘法器（115）的值。 提供主控制器（190），其被配置为选择性地将累积值存储在数据存储器（100）中用于进一步处理或输出累积值。 与数据存储器（100）和系数存储器（105）通信的地址和控制块（125）保持适合要执行的滤波器的值。 地址和控制块（125）具有两组用于级联地保持第一预定数字滤波器和第二预定数字滤波器的值的第一组寄存器。 该方法将地址和控制块（125）中的数据的当前写入地址保持为循环列表，其中循环列表具有等于预定数量的滤波器抽头的大小。 该方法将来自第一端口的数据的第一读取地址作为先入先出队列，将来自第二端口的数据的第二读取地址作为先到先出的堆栈，以及系数读取地址 作为循环列表。

公开(公告)号：WO2008010908A2

公开(公告)日：2008-01-24

申请号：PCT/US2007/015281

申请日：2007-07-09

Applicant: QUICKFILTER TECHNOLOGIES, INC. ,  LEONARD, Jeramy ,  ELLIOTT, William ,  MAGDEBURGER, Thomas

Inventor： LEONARD, Jeramy ,  ELLIOTT, William ,  MAGDEBURGER, Thomas

IPC: H03M1/66

CPC classification number: H03H17/0294 ,  H03H17/06

Abstract: An analog-to-digital conversion system has an analog-to-digital converter (300) and a digital-filter system (100). The digital-filter system (100) is connected to the output of the analog-to-digital converter (300). A processor (310) is connected to the output of the digital-filter system (100) so that the processor (310) transparently receives filtered sample data in the native format of the analog-to-digital converter (300). An FIR filter circuit (130) in the digital-filter system (100) is connected to receive data from, and output filtered data to, a sample capture and data-type conversion circuit (120) connected between the analog-to-digital converter (300) and the processor (310). A configuration and control-register circuit (110) is connected to the circuit for sample collection and data-type conversion (120), and to the FIR filter circuit (130), for selectively controlling the operation of the digital filter system (100) according to parameters for data conversion and filter operation passed to the configuration and control-register circuit (110) over a serial interface.

Abstract translation: 模拟 - 数字转换系统具有模数转换器（300）和数字滤波器系统（100）。 数字滤波器系统（100）连接到模拟 - 数字转换器（300）的输出端。 处理器（310）连接到数字滤波器系统（100）的输出，使得处理器（310）以模数转换器（300）的原生格式透明地接收滤波的采样数据。 数字滤波器系统（100）中的FIR滤波器电路（130）被连接以从样本捕获和数据类型转换电路（120）接收数据并将其输出到连接在模数转换器 （300）和处理器（310）。 配置和控制寄存器电路（110）连接到用于采样和数据类型转换的电路（120），并连接到FIR滤波器电路（130），用于选择性地控制数字滤波器系统（100）的操作， 根据用于通过串行接口传递到配置和控制寄存器电路（110）的数据转换和滤波器操作的参数。

公开(公告)号：WO2007032895A2

公开(公告)日：2007-03-22

申请号：PCT/US2006/033469

申请日：2006-08-29

Applicant: QUICKFILTER TECHNOLOGIES, INC. ,  MAGDEBURGER, Thomas ,  HEADLEY, Aaron

Inventor： MAGDEBURGER, Thomas ,  HEADLEY, Aaron

IPC: G06F7/00

CPC classification number: G06F13/385

Abstract: A serial interface controller (200) provides for transferring data between a data source having a least one channel (110) and a processor. The serial interface controller (200) has a plurality of control registers (220); the control registers (220) in turn include a data structure for configuring the serial interface controller (200) for a data transfer. That data structure further comprises a field for selectively setting the serial interface controller (200) in its run mode or its configuration mode; a field for storing the I/O mode of the serial interface controller (200); a field for storing the address of the active data channel; and, a field for storing the system clock rate. In the preferred embodiment, the control registers (220) include fields for device identification, a flag for the run or configure mode, a I/O-mode control, a value for the channels active (in multi-channel implementations), the data source clock rate, the ADC clock rate, channel-status flags, the CIC decimation rate, the number of taps for FIR filters, and the filter coefficients corresponding to the number of FIR taps in a particular data source.

Abstract translation: 串行接口控制器（200）提供用于在具有至少一个通道（110）的数据源和处理器之间传送数据。 串行接口控制器（200）具有多个控制寄存器（220）; 控制寄存器（220）又包括用于配置用于数据传送的串行接口控制器（200）的数据结构。 该数据结构还包括用于选择性地将串行接口控制器（200）设置为其运行模式或其配置模式的字段; 用于存储串行接口控制器（200）的I / O模式的字段; 用于存储活动数据信道的地址的字段; 以及用于存储系统时钟速率的字段。 在优选实施例中，控制寄存器（220）包括用于设备识别的字段，用于运行或配置模式的标志，I / O模式控制，用于通道活动的（多通道实现中）的值，数据 源时钟速率，ADC时钟速率，信道状态标志，CIC抽取率，FIR滤波器的抽头数，以及与特定数据源中FIR抽头数量相对应的滤波器系数。

公开(公告)号：WO2007027692A2

公开(公告)日：2007-03-08

申请号：PCT/US2006/033725

申请日：2006-08-29

Applicant: QUICKFILTER TECHNOLOGIES, INC. ,  MAGDEBURGER, Thomas ,  BEST, Dennis

Inventor： MAGDEBURGER, Thomas ,  BEST, Dennis

IPC: H03M7/00

CPC classification number: G06F7/5443

Abstract: An integrated circuit for implementing a digital filter has a data memory (100); the data memory (100) having two ports (210, 220) to permit the access of two data samples at the same time, and a coefficient memory (105) for storing filter coefficients. A first adder (110) adds data samples from first and second data memory ports (210, 220); a multiplier (115) multiplies a value from the first adder (110) by a value from the coefficient memory (105); and, a second adder accumulates values from the multiplier (115). A master controller (190) is provided configured for selectively storing the accumulated values in the data memory (100) for further processing or outputting the accumulated values. An address and control block (125) communicating with the data memory (100) and the coefficient memory (105) holds values appropriate to the filter to be executed. The address and control block (125) has two sets of a first set of registers for holding values for a first pre-determined digital filter and a second pre-determined digital filter in cascade. The method maintains a current write address for data in the address and control block (125) as a circular list, where the circular list has a size equal to a predetermined number of filter taps;. The method maintains a first read address for data from the first port as a first-in-first-out queue, a second read address for data from the second port as a last-in-first-out stack, and a coefficient read address as a circular list.

Abstract translation: 一种用于实现数字滤波器的集成电路具有数据存储器（100）; 数据存储器（100）具有允许同时访问两个数据样本的两个端口（210,220）和用于存储滤波器系数的系数存储器（105）。 第一加法器（110）将来自第一和第二数据存储器端口（210,220）的数据样本相加; 乘法器（115）将来自第一加法器（110）的值与来自系数存储器（105）的值相乘; 并且第二加法器累加来自乘法器（115）的值。 提供主控制器（190），其被配置为选择性地将累积值存储在数据存储器（100）中用于进一步处理或输出累积值。 与数据存储器（100）和系数存储器（105）通信的地址和控制块（125）保持适合要执行的滤波器的值。 地址和控制块（125）具有两组用于级联地保持第一预定数字滤波器和第二预定数字滤波器的值的第一组寄存器。 该方法将地址和控制块（125）中的数据的当前写入地址保持为循环列表，其中循环列表具有等于预定数量的滤波器抽头的大小。 该方法将来自第一端口的数据的第一读取地址作为先入先出队列，将来自第二端口的数据的第二读取地址作为先到先出的堆栈，以及系数读取地址 作为循环列表。