公开(公告)号：WO2007024469A2

公开(公告)日：2007-03-01

申请号：PCT/US2006030822

申请日：2006-08-08

Applicant: FREESCALE SEMICONDUCTOR INC ,  TRACY CLARENCE J ,  JOHNSON ERIC S ,  MANIAR PAPU D

Inventor： TRACY CLARENCE J ,  JOHNSON ERIC S ,  MANIAR PAPU D

IPC: H01L21/20

CPC classification number: H01L21/76251 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02658

Abstract: A method of forming III-V epitaxy (42) on a germanium-on-insulator (GOI) substrate 40having a bonded layer (14) and a handle substrate(12) begins with measuring a lattice parameter of the bonded layer at a first temperature. The lattice parameter of the bonded layer, which is a function of a coefficient of thermal expansion (CTE) of the handle substrate, is then calculated at an epitaxial growth temperature. An epitaxial composition is selected from a class of III-V material for epitaxial growth overlying the bonded layer, wherein the selected epitaxial composition is adjusted to have a lattice parameter that approximates the calculated lattice parameter of the bonded layer at the epitaxial growth temperature. An epitaxial layer (42) can then be grown over the bonded layer (14) with use of the adjusted epitaxial composition, producing a substantially defect-free III-V epitaxial layer. Furthermore, an improved defectivity is claimed when the epitaxial layer's CTE is approximately similar to that of the handle substrate.

Abstract translation: 在具有键合层（14）和处理衬底（12）的绝缘体上锗（GOI）衬底40上形成III-V外延（42）的方法开始于在第一温度下测量键合层的晶格参数 。 然后在外延生长温度下计算作为处理衬底的热膨胀系数（CTE）的函数的接合层的晶格参数。 从用于外延生长的一类III-V族材料中选择外延组合物，其中所述外延组合物被调整为具有近似计算在外延生长温度下所述键合层的晶格参数的晶格参数。 然后可以使用调节后的外延组合物在外延层（14）上生长外延层（42），从而产生基本无缺陷的III-V外延层。 此外，当外延层的CTE大致类似于处理衬底的CTE时，声称改善的缺陷率。

公开(公告)号：WO2006023027A1

公开(公告)日：2006-03-02

申请号：PCT/US2005/021498

申请日：2005-06-16

Applicant: FREESCALE SEMICONDUCTOR, INC. ,  THOMAS, Shawn, G. ,  MANIAR, Papu, D. ,  ILDEREM, Vida

Inventor： THOMAS, Shawn, G. ,  MANIAR, Papu, D. ,  ILDEREM, Vida

IPC: H01L21/00

CPC classification number: H01L21/022 ,  H01L21/02164 ,  H01L21/02175 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02617 ,  H01L21/02664 ,  H01L21/28255 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/513 ,  H01L29/517 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatus are provided for depositing a layer of pure germanium (12) can on a silicon substrate (11). This germanium layer is very thin, on the order of about 14 A, and is less than the critical thickness for pure germanium on silicon. The germanium layer (12) serves as an intermediate layer between the silicon substrate (11) and the high k gate layer (13), which is deposited on the germanium layer (12). The germanium layer (12) helps to avoid the development of an oxide interfacial layer during the application of the high k material. Application of the germanium intermediate layer in a semiconductor structure results in a high k gate functionality without: the drawbacks of series capacitance due to oxide impurities. The germanium layer (12) further improves mobility.

Abstract translation: 提供了用于在硅衬底（11）上沉积纯锗（12）罐的层的方法和装置。 该锗层非常薄，约为14A，并且小于硅上的纯锗的临界厚度。 锗层（12）用作沉积在锗层（12）上的硅衬底（11）和高k栅极层（13）之间的中间层。 锗层（12）有助于在施加高k材料期间避免氧化物界面层的发展。 锗中间层在半导体结构中的应用导致高k栅极功能，而没有：由于氧化物杂质引起的串联电容的缺点。 锗层（12）进一步提高了移动性。

公开(公告)号：WO2007067838A3

公开(公告)日：2007-12-21

申请号：PCT/US2006060936

申请日：2006-11-15

Applicant: MOTOROLA INC ,  THOMAS SHAWN G ,  ILDEREM VIDA ,  MANIAR PAPU D ,  MARACAS GEORGE N

Inventor： THOMAS SHAWN G ,  ILDEREM VIDA ,  MANIAR PAPU D ,  MARACAS GEORGE N

IPC: G06K19/06 ,  G08B13/14

CPC classification number: H01L23/645 ,  H01F17/0006 ,  H01F2017/0046 ,  H01L23/5227 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method is provided for making an inductor comprising forming a catalytic material (14) over a substrate (12); and creating a network of one dimensional nanostructures (30) on the catalytic material, the network providing an inductance when a voltage is applied thereacross. This inductor is described in three applications: as an on-chip inductor for electronic circuitry, as a magnetic sensor, and as an environmental sensor. Several embodiments are described herein for forming networks of nanostructures on or above the substrate that provide an inductance having a high Q and a reduced die size for RF circuits. Several embodiments are also described for use of the nanostructure to sense gasses, radiation, a magnetic field, and the like.

Abstract translation: 提供了一种用于制造电感器的方法，包括在衬底（12）上形成催化材料（14）; 以及在所述催化材料上形成一维纳米结构（30）的网络，所述网络在施加电压时提供电感。 该电感器在三个应用中被描述：作为用于电子电路的片上电感器，作为磁传感器，以及作为环境传感器。 本文描述了几个实施例，用于在衬底上或上方形成纳米结构网络，其提供具有高Q值的电感和用于RF电路的减小的管芯尺寸。 还描述了使用纳米结构来感测气体，辐射，磁场等的几个实施例。

公开(公告)号：WO2007067838A2

公开(公告)日：2007-06-14

申请号：PCT/US2006/060936

申请日：2006-11-15

Applicant: MOTOROLA INC. ,  THOMAS, Shawn, G. ,  ILDEREM, Vida ,  MANIAR, Papu, D. ,  MARACAS, George, N.

Inventor： THOMAS, Shawn, G. ,  ILDEREM, Vida ,  MANIAR, Papu, D. ,  MARACAS, George, N.

IPC: H01L21/64

CPC classification number: H01L23/645 ,  H01F17/0006 ,  H01F2017/0046 ,  H01L23/5227 ,  H01L23/53276 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A method is provided for making an inductor comprising forming a catalytic material (14) over a substrate (12); and creating a network of one dimensional nanostructures (30) on the catalytic material, the network providing an inductance when a voltage is applied thereacross. This inductor is described in three applications: as an on-chip inductor for electronic circuitry, as a magnetic sensor, and as an environmental sensor. Several embodiments are described herein for forming networks of nanostructures on or above the substrate that provide an inductance having a high Q and a reduced die size for RF circuits. Several embodiments are also described for use of the nanostructure to sense gasses, radiation, a magnetic field, and the like.

Abstract translation: 提供了一种用于制造电感器的方法，该方法包括在衬底（12）上形成催化材料（14）; 以及在催化材料上形成一维纳米结构（30）的网络，该网络在其上施加电压时提供电感。 该电感器在三个应用中有所描述：作为电子电路的片上电感器，磁性传感器和环境传感器。 本文描述了用于在衬底上或上方形成纳米结构网络的若干实施例，其为RF电路提供具有高Q值和减小的裸片尺寸的电感。 还描述了使用纳米结构来感测气体，辐射，磁场等的几个实施例。

公开(公告)号：WO2007024469A3

公开(公告)日：2007-03-01

申请号：PCT/US2006/030822

申请日：2006-08-08

Applicant: FREESCALE SEMICONDUCTOR ,  TRACY, Clarence J. ,  JOHNSON, Eric S. ,  MANIAR, Papu D.

Inventor： TRACY, Clarence J. ,  JOHNSON, Eric S. ,  MANIAR, Papu D.

IPC: H01L21/20 ,  H01L21/36

Abstract: A method of forming III-V epitaxy (42) on a germanium-on-insulator (GOI) substrate 40having a bonded layer (14) and a handle substrate(12) begins with measuring a lattice parameter of the bonded layer at a first temperature. The lattice parameter of the bonded layer, which is a function of a coefficient of thermal expansion (CTE) of the handle substrate, is then calculated at an epitaxial growth temperature. An epitaxial composition is selected from a class of III-V material for epitaxial growth overlying the bonded layer, wherein the selected epitaxial composition is adjusted to have a lattice parameter that approximates the calculated lattice parameter of the bonded layer at the epitaxial growth temperature. An epitaxial layer (42) can then be grown over the bonded layer (14) with use of the adjusted epitaxial composition, producing a substantially defect-free III-V epitaxial layer. Furthermore, an improved defectivity is claimed when the epitaxial layer's CTE is approximately similar to that of the handle substrate.