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公开(公告)号：WO2010004245A1
公开(公告)日：2010-01-14
申请号：PCT/GB2009/001318
申请日：2009-05-27
Applicant: CAMBRIDGE CONSULTANTS LIMITED , MORFEY, Alistair, Guy
Inventor： MORFEY, Alistair, Guy
IPC: G06F9/30
CPC classification number: G06F12/1491 , G06F9/30189 , G06F9/3861 , G06F9/48 , G06F9/4843 , Y02D10/13
Abstract: A processor (10) is disclosed which is configured to execute a push immediate instruction specifying a plurality of immediate values to be pushed to a stack. Different instruction formats for different numbers and/or sizes of immediate operands are provided. The operands may be binary operands. The instruction is interruptible between individual push operations for processing of external interrupts or internal exceptions.
Abstract translation: 公开了一种处理器（10），其被配置为执行指定要推送到堆栈的多个立即值的推即用指令。 提供了不同数量和/或大小的立即操作数的不同指令格式。 操作数可以是二进制操作数。 在用于处理外部中断或内部异常的各个推送操作之间可以中断该指令。
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公开(公告)号：WO2003048978A3
公开(公告)日：2003-06-12
申请号：PCT/GB2002/005428
申请日：2002-12-04
Applicant: CAMBRIDGE CONSULTANTS LIMITED , MORFEY, Alistair, Guy , RAMSDALE, Timothy, James , WILLIAMS, Richard, Penry
IPC: G06F17/50
Abstract: A processor, suitable for embedded applications, is disclosed comprising a processor core and peripheral devices. One of these devices is a memory management unit allowing the designer of an application specific integrated circuit (ASIC) embodying the processor to tailor the interface between the processor and memory devices according to the intented memory configuration of the processor. Also disclosed is a computer-aided method of disigning such a processor, allowing a user to specify at descriptor level a Harvard or von Neuman memory interface between the processor and memory devices.
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公开(公告)号：WO2010004243A2
公开(公告)日：2010-01-14
申请号：PCT/GB2009/001314
申请日：2009-05-27
Applicant: CAMBRIDGE CONSULTANTS LIMITED , MORFEY, Alistair, Guy
Inventor： MORFEY, Alistair, Guy
IPC: G06F9/48
CPC classification number: G06F12/1491 , G06F9/30189 , G06F9/3861 , G06F9/48 , G06F9/4843 , Y02D10/13
Abstract: This invention relates to a data processing apparatus comprising: a processor (10); a first memory location, the processor (10) being adapted to control whether the operation of the processor may be interrupted in dependence on a value stored in the first memory location; and a second memory location, the processor (10) being adapted a) to store a value in the second memory location following an event that is related to the value stored in the first memory location, and b) otherwise to store a value in the second memory location that is not related to the value stored in the first memory location. This invention also relates to a method of data processing.
Abstract translation: 数据处理设备技术领域本发明涉及一种数据处理设备，包括：处理器（10）;处理器 第一存储器位置，所述处理器（10）适于根据存储在所述第一存储器位置中的值来控制是否可以中断所述处理器的所述操作; 以及第二存储器位置，所述处理器（10）适于：a）在与存储在所述第一存储器位置中的所述值相关的事件之后，将值存储在所述第二存储器位置中;以及b）否则将所述值存储在 第二存储器位置与存储在第一存储器位置中的值无关。 本发明还涉及一种数据处理方法。
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公开(公告)号：WO2006120470A2
公开(公告)日：2006-11-16
申请号：PCT/GB2006/001756
申请日：2006-05-12
Applicant: CAMBRIDGE CONSULTANTS LIMITED , MORFEY, Alistair, Guy , SWEPSON, Karl, Leighton , JOHNSON, Neil, Edward , COOPER, Martin, David , MYCROFT, Alan
Inventor： MORFEY, Alistair, Guy , SWEPSON, Karl, Leighton , JOHNSON, Neil, Edward , COOPER, Martin, David , MYCROFT, Alan
IPC: G06F9/38
CPC classification number: G06F9/3017 , G06F8/4434 , G06F9/30032 , G06F9/30101 , G06F9/30149 , G06F9/30167 , G06F9/30174 , G06F9/30178
Abstract: The present invention relates to a processor which comprises an instruction set for execution on the processor, a processor architecture and a memory, wherein the instruction set and the processor architecture comprise characteristics which have been specifically tailored to ensure that the code density compiled for execution at least in part on the processor memory is relatively high. The invention -alsorelates-tο-a compiler.-The-invention-extends to a system comprising a master computer; one or more control pods; and one or more integrated circuits, each comprising one or more processors; wherein the master computer is operable to interact with any of said processors via said one or more control pods.
Abstract translation: 本发明涉及一种处理器，其包括用于在处理器上执行的指令集，处理器架构和存储器，其中指令集和处理器架构包括专门定制的特性，以确保编译为执行的代码密度 处理器内存最少部分在于相对较高。 本发明是一种编译器 - 本发明 - 扩展到包括主计算机的系统; 一个或多个控制舱; 以及一个或多个集成电路，每个集成电路包括一个或多个处理器; 其中所述主计算机可操作以经由所述一个或多个控制盒与任何所述处理器进行交互。
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公开(公告)号：WO2003048978A2
公开(公告)日：2003-06-12
申请号：PCT/GB2002/005428
申请日：2002-12-04
Applicant: CAMBRIDGE CONSULTANTS LIMITED , MORFEY, Alistair, Guy , RAMSDALE, Timothy, James , WILLIAMS, Richard, Penry
IPC: G06F17/50
CPC classification number: G06F17/5045
Abstract: A processor, suitable for embedded applications, is disclosed comprising a processor core and peripheral devices. One of these devices is a memory management unit allowing the designer of an application specific integrated circuit (ASIC) embodying the processor to tailor the interface between the processor and memory devices according to the intented memory configuration of the processor. Also disclosed is a computer-aided method of disigning such a processor, allowing a user to specify at descriptor level a Harvard or von Neuman memory interface between the processor and memory devices.
Abstract translation: 公开了一种适用于嵌入式应用的处理器，其包括处理器核心和外围设备。 这些设备中的一个是存储器管理单元，其允许体现处理器的专用集成电路（ASIC）的设计者根据处理器的有意的存储器配置来调整处理器和存储器件之间的接口。 还公开了一种控制这种处理器的计算机辅助方法，允许用户在描述符级别指定处理器和存储器设备之间的哈佛或冯诺曼存储器接口。
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Patent Agency Ranking
公开(公告)号：WO0163219A3
公开(公告)日：2002-03-21
申请号：PCT/EP0102087
申请日：2001-02-23
Applicant: CAMBRIDGE CONSULTANTS , CLOUSTON ERIC NICOL , MORFEY ALISTAIR GUY
Inventor： CLOUSTON ERIC NICOL , MORFEY ALISTAIR GUY
IPC: G01F23/284
CPC classification number: G01F23/284 , G01F22/00
Abstract: A time domain reflectometry probe for fluid level measurement has a first portion which is vertical and a second portion which is horizontal. The horizontal portion has greater resolution than the vertical portion to give increased accuracy over a region of the measurement range. The first and second portions can also be at acute angles to the vertical and horizontal respectively.
Abstract translation: 用于液位测量的时域反射探针具有垂直的第一部分和水平的第二部分。 水平部分具有比垂直部分更高的分辨率，以在测量范围的区域上提供更高的精度。 第一和第二部分也可以分别与垂直和水平成锐角。
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公开(公告)号：WO2010004240A1
公开(公告)日：2010-01-14
申请号：PCT/GB2009/001309
申请日：2009-05-27
Applicant: CAMBRIDGE CONSULTANTS LIMITED , MORFEY, Alistair, Guy , SWEPSON, Karl, Leighton , LLOYD, Peter, Giles
Inventor： MORFEY, Alistair, Guy , SWEPSON, Karl, Leighton , LLOYD, Peter, Giles
CPC classification number: G06F12/1491 , G06F9/30189 , G06F9/3861 , G06F9/48 , G06F9/4843 , Y02D10/13
Abstract: This invention relates to a data processing apparatus (1) including a processor (10) adapted to operate under control of an executable comprising instructions, and in any of a plurality of operating modes including a non-privileged mode and a privileged mode, the apparatus (1) comprising: means for storing a plurality of stacks; a first stack pointer register for storing a pointer to an address in a first of said stacks; a second stack pointer register for storing a pointer to an address in a second of said stacks, wherein said processing apparatus is adapted to use said second stack pointer when said processor is operating in either the non-privileged mode or the privileged mode; and means for transferring operation of said processor from the non-privileged mode to the privileged mode in response to at least one of said instructions. This invention also relates to a method of operating a data processing apparatus.
Abstract translation: 本发明涉及一种包括处理器（10）的处理器（10），该处理器（10）适于在包括指令的可执行程序的控制下操作，并且在包括非特权模式和特权模式的多种操作模式中的任一种中，所述装置 （1）包括：用于存储多个堆叠的装置; 第一堆栈指针寄存器，用于存储指向第一堆栈中的地址的指针; 第二堆栈指针寄存器，用于存储指向第二堆栈中的第二个地址的指针，其中所述处理装置适于当所述处理器以非特权模式或特权模式操作时使用所述第二堆栈指针; 以及用于响应于所述指令中的至少一个将所述处理器的操作从非特权模式转移到特权模式的装置。 本发明还涉及一种操作数据处理装置的方法。
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公开(公告)号：WO2006120470A3
公开(公告)日：2007-09-07
申请号：PCT/GB2006001756
申请日：2006-05-12
Applicant: CAMBRIDGE CONSULTANTS , MORFEY ALISTAIR GUY , SWEPSON KARL LEIGHTON , JOHNSON NEIL EDWARD , COOPER MARTIN DAVID , MYCROFT ALAN
Inventor： MORFEY ALISTAIR GUY , SWEPSON KARL LEIGHTON , JOHNSON NEIL EDWARD , COOPER MARTIN DAVID , MYCROFT ALAN
IPC: G06F9/30
CPC classification number: G06F9/3017 , G06F8/4434 , G06F9/30032 , G06F9/30101 , G06F9/30149 , G06F9/30167 , G06F9/30174 , G06F9/30178
Abstract: The present invention relates to a processor which comprises an instruction set for execution on the processor, a processor architecture and a memory, wherein the instruction set and the processor architecture comprise characteristics which have been specifically tailored to ensure that the code density compiled for execution at least in part on the processor memory is relatively high. The invention -alsorelates-t?-a compiler.-The-invention-extends to a system comprising a master computer; one or more control pods; and one or more integrated circuits, each comprising one or more processors; wherein the master computer is operable to interact with any of said processors via said one or more control pods.
Abstract translation: 本发明涉及一种处理器，其包括用于在处理器上执行的指令集，处理器架构和存储器，其中指令集和处理器架构包括专门定制的特性，以确保编译为执行的代码密度 处理器内存最少部分在于相对较高。 本发明是一种编译器 - 本发明 - 扩展到包括主计算机的系统; 一个或多个控制舱; 以及一个或多个集成电路，每个集成电路包括一个或多个处理器; 其中所述主计算机可操作以经由所述一个或多个控制盒与任何所述处理器进行交互。
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公开(公告)号：WO03048978A8
公开(公告)日：2004-10-07
申请号：PCT/GB0205428
申请日：2002-12-04
Applicant: CAMBRIDGE CONSULTANTS , MORFEY ALISTAIR GUY , RAMSDALE TIMOTHY JAMES , WILLIAMS RICHARD PENRY
Inventor： MORFEY ALISTAIR GUY , RAMSDALE TIMOTHY JAMES , WILLIAMS RICHARD PENRY
IPC: G06F17/50
CPC classification number: G06F17/5045
Abstract: A processor, suitable for embedded applications, is disclosed comprising a processor core and peripheral devices. One of these devices is a memory management unit allowing the designer of an application specific integrated circuit (ASIC) embodying the processor to tailor the interface between the processor and memory devices according to the intented memory configuration of the processor. Also disclosed is a computer-aided method of disigning such a processor, allowing a user to specify at descriptor level a Harvard or von Neuman memory interface between the processor and memory devices.
Abstract translation: 公开了一种适用于嵌入式应用的处理器，其包括处理器核心和外围设备。 这些设备中的一个是存储器管理单元，其允许体现处理器的专用集成电路（ASIC）的设计者根据处理器的有意的存储器配置来调整处理器和存储器件之间的接口。 还公开了一种控制这种处理器的计算机辅助方法，允许用户在描述符级别指定处理器和存储器设备之间的哈佛或冯诺曼存储器接口。
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公开(公告)号：WO9609583A2
公开(公告)日：1996-03-28
申请号：PCT/GB9502283
申请日：1995-09-25
Applicant: CAMBRIDGE CONSULTANTS , BARLOW STEPHEN JOHN , MORFEY ALISTAIR GUY , COLLIER JAMES DIGBY YARLET
Inventor： BARLOW STEPHEN JOHN , MORFEY ALISTAIR GUY , COLLIER JAMES DIGBY YARLET
CPC classification number: G06F7/57 , G06F1/3203 , G06F1/3237 , G06F9/30 , G06F9/30014 , G06F9/30032 , G06F9/3005 , G06F9/30083 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F9/30167 , G06F9/322 , G06F9/324 , G06F9/3869 , G06F11/2236 , G06F11/3648 , G06F11/3656 , G06F15/7832 , Y02D10/128 , Y02D50/20
Abstract: An integrated circuit contains (102) a microprocessor core (100), program memory (104) and separate data storage (106, 108), together with analogue and digital signal processing circuitry (110). The ALU (302) is 16 bits wide, but a 32-bit shift unit (312) is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. External pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test data or working data as necessary. The serial interface has four wires (SER IN, SER OUT, SER-CLK, SER LOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space (104-110) of the processor core (100), without specific program control. Within each processor cycle, the processor circuitry is divided into plural stages, and latches are interposed between the stages to minimise power consumption.
Abstract translation: 集成电路与模拟和数字信号处理电路（110）一起包含（102）微处理器核心（100），程序存储器（104）和单独的数据存储器（106,108）。 ALU（302）是16位宽，但是使用一对16位寄存器来提供32位移位单元（312）。 处理器具有固定长度的指令格式，其中指令集包括在多个周期内使用移位单元的乘法和除法运算。 不提供中断。 集成电路的外部引脚允许单步和其他调试操作，以及允许外部通信测试数据或工作数据的串行接口（SIF）。 串行接口具有四条线（SER IN，SER OUT，SER-CLK，SER LOADB），允许与主设备进行握手，以及 允许直接访问处理器核心（100）的存储空间（104-110），而无需特定的程序控制。 在每个处理器周期内，处理器电路被分成多个级，并且锁存器插在两个级之间以使功耗最小化。
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