公开(公告)号：WO02073658A3

公开(公告)日：2003-04-03

申请号：PCT/IN0200039

申请日：2002-03-11

Applicant: INDIAN INST SCIENT ,  BHAT NAVAKANTA ,  MUKHERJEE SUGATO

Inventor： BHAT NAVAKANTA ,  MUKHERJEE SUGATO

IPC: G11C7/00 ,  G11C7/06 ,  G11C11/4091 ,  G11C11/413 ,  G11C29/50 ,  H01L20060101

CPC classification number: G11C11/4091 ,  G11C7/06 ,  G11C7/065 ,  G11C11/413 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2254

Abstract: A novel technique for the enhancement of yield and speed of semiconductor integrated circuits using post fabrication transistor mismatch compensation circuitry is proposed. The system comprises of sense amplifier SA, multiplexer MUX, delay elements Delay-1, Delay-2, and provision for hardwiring fast and slow circuits during packaging. The sense amplifier firing path is split into slow and fast path and the multiplexer can select one of these paths. The memory circuits are tested after fabrication to assess whether they could be partitioned as slow or fast circuits and accordingly an appropriate path is selected by the multiplexer.

Abstract translation: 提出了一种使用后制造晶体管失配补偿电路提高半导体集成电路的产量和速度的新颖技术。 该系统包括读出放大器SA，多路复用器MUX，延迟元件Delay-1，Delay-2，以及用于在封装期间硬连线快速和慢速电路。 读出放大器触发路径被分成慢速和快速的路径，并且多路复用器可以选择这些路径之一。 存储器电路在制造之后进行测试以评估它们是否可以被分割为慢速或快速电路，并且因此多路复用器选择适当的路径。

公开(公告)号：WO2002073658A2

公开(公告)日：2002-09-19

申请号：PCT/IN2002/000039

申请日：2002-03-11

Applicant: INDIAN INSTITUTE OF SCIENCE ,  BHAT, Navakanta ,  MUKHERJEE, Sugato

Inventor： BHAT, Navakanta ,  MUKHERJEE, Sugato

IPC: H01L

CPC classification number: G11C11/4091 ,  G11C7/06 ,  G11C7/065 ,  G11C11/413 ,  G11C29/026 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2254

Abstract: A novel technique for the enhancement of yield and speed of semiconductor integrated circuits using post fabrication transistor mismatch compensation circuitry is proposed. The system is novel because it recognizes that no matter what, the transistor mismatch is statistical in nature and hence it is prudent to exploit the nature of the distribution to get fast and slow circuits rather than make all circuits slow to meet 6σ design index. The system comprises of sense amplifier, multiplexer, delay elements, and provision for hardwiring fast and slow circuits during packaging. The sense amplifier firing path is split into slow and fast path and the multiplexer can select one of these. The memory circuits are tested after fabrication to assess whether they could be partitioned as slow or fast circuits and accordingly an appropriate path is selected by the multiplexer. This path is then hardwired during packaging by connecting the select input of multiplexer to VDD or GND.

Abstract translation: 提出了一种使用后制造晶体管失配补偿电路提高半导体集成电路的产量和速度的新颖技术。 该系统是新颖的，因为它意识到无论什么，晶体管不匹配都是统计学的，因此，谨慎地利用分布的性质来获得快速和慢速的电路，而不是使所有电路缓慢达到6西格玛设计指标。 该系统包括读出放大器，多路复用器，延迟元件，以及用于在封装期间硬连线快速和慢速电路。 感测放大器点火路径分为慢速和快速路径，多路复用器可以选择其中之一。 存储器电路在制造之后进行测试以评估它们是否可以被分割为慢速或快速电路，并且因此多路复用器选择适当的路径。 通过将多路复用器的选择输入连接到VDD或GND，在封装过程中，此路径将被硬连线。