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    METHOD AND APPARATUS FOR HARDWARE XML ACCELERATION
    1.
    发明申请
    METHOD AND APPARATUS FOR HARDWARE XML ACCELERATION 审中-公开
    硬件XML加速的方法和装置

    公开(公告)号：WO2007058949A3

    公开(公告)日：2007-07-19

    申请号：PCT/US2006043811

    申请日：2006-11-08

    Applicant: SUN MICROSYSTEMS INC ,  BEHRENS JOCHEN ,  DIGNUM MARCELINO M ,  SELTZER WAYNE F ,  ZAUMEN WILLIAM T ,  PETRY JOHN P ,  PERICAS-GEERTSEN SANTIAGO M ,  NAG BISWADEEP

    Inventor： BEHRENS JOCHEN ,  DIGNUM MARCELINO M ,  SELTZER WAYNE F ,  ZAUMEN WILLIAM T ,  PETRY JOHN P ,  PERICAS-GEERTSEN SANTIAGO M ,  NAG BISWADEEP

    IPC: G06F17/30

    CPC classification number: G06F15/7842

    Abstract: A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), hardware XML parser units, cryptographic units, and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or parsed in segments (e.g., as it is received). A parser unit parses a document (or segment) character by character, validates the characters, assembles tokens, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g., memory, bus) are greatly reduced, thereby providing significantly improved XML processing and security processing throughput.

    Abstract translation: 一种用于加速结构化文档处理的方法和装置。 硬件XML加速器包括一个或多个处理器（例如，CMT处理器），硬件XML解析器单元，加密单元和各种接口（例如，到存储器，网络，通信总线）。 XML文档可以被整体处理或以段（例如，被接收）来解析。 解析器单元按字符分析文档（或段），验证字符，汇编令牌，提取数据，生成令牌标题（描述令牌和数据），并转发令牌标题和数据以供应用程序使用。 加密单元可以通过提供加密/解密功能，计算数字签名等来实施Web安全性，XML安全性或某些其他安全性方案。软件处理，总线利用和延迟（例如，存储器，总线）大大降低，从而显着提供 改进的XML处理和安全处理吞吐量。

    MAXIMUM CURRENT LIMITING METHOD AND APPARATUS
    2.
    发明申请
    MAXIMUM CURRENT LIMITING METHOD AND APPARATUS 审中-公开
    最大电流限制方法和装置

    公开(公告)号：WO2012075223A1

    公开(公告)日：2012-06-07

    申请号：PCT/US2011/062775

    申请日：2011-12-01

    Applicant: ADVANCED MICRO DEVICES, INC. ,  NAFFZIGER, Samuel D. ,  PETRY, John P. ,  BONDALAPATI, Kiran

    Inventor： NAFFZIGER, Samuel D. ,  PETRY, John P. ,  BONDALAPATI, Kiran

    IPC: G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/26 ,  G06F1/3203 ,  Y02D10/126

    Abstract: The maximum current is limited in a multi-processor core system by monitoring the latest power consumption in the processor cores, in order to prevent a system shutdown as a result of an over-current event. If the sum of the latest power of the processor cores exceeds a threshold limit, a performance state (P-state) limit is enforced in the processor cores. The P-state limit causes a P-state change to a lower frequency, voltage and thus a lower current.

    Abstract translation: 通过监控处理器核心中的最新功耗，多处理器核心系统中的最大电流受到限制，以防止由于过电流事件导致系统关闭。 如果处理器核心的最新功率的总和超过阈值限制，则在处理器核心中执行性能状态（P状态）限制。 P态极限导致P态变化到较低的频率，电压，从而导致较低的电流。

    MANAGING MULTIPLE OPERATING POINTS FOR STABLE VIRTUAL FREQUENCIES
    3.
    发明申请
    MANAGING MULTIPLE OPERATING POINTS FOR STABLE VIRTUAL FREQUENCIES 审中-公开
    管理稳定的虚拟频率的多个操作要点

    公开(公告)号：WO2011163261A1

    公开(公告)日：2011-12-29

    申请号：PCT/US2011/041291

    申请日：2011-06-21

    Applicant: ADVANCED MICRO DEVICES, INC. ,  NAFFZIGER, Samuel, D. ,  PETRY, John, P. ,  HUGHES, William, A.

    Inventor： NAFFZIGER, Samuel, D. ,  PETRY, John, P. ,  HUGHES, William, A.

    IPC: G06F1/32

    CPC classification number: G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: A system and method for managing multiple discrete operating points to create a stable virtual operating point. One or more functional blocks within a processor produces data corresponding to an activity level associated with the respective functional block. A power manager determines a power consumption value based on the data once every given sample interval. In addition, the power manager determines a signed accumulated difference over time between a thermal design power (TDP) and the power consumption value. The power manager selects a next power-performance state (P-state) based on comparisons of the signed accumulated difference and given thresholds. Transitioning between P-states in this manner while the workload does not significantly change causes the processor to operate at a virtual operating point between supported discrete operating points.

    Abstract translation: 一种用于管理多个离散工作点以创建稳定的虚拟操作点的系统和方法。 处理器内的一个或多个功能块产生对应于与相应功能块相关联的活动级别的数据。 功率管理器基于每个给定采样间隔一次的数据来确定功耗值。 此外，功率管理器确定在热设计功率（TDP）和功耗值之间随时间的经签名的积分差。 功率管理器基于签名累积差和给定阈值的比较来选择下一个功率性能状态（P状态）。 以这种方式在P状态之间转换，而工作负载不会显着变化，导致处理器在支持的离散工作点之间的虚拟工作点运行。

    METHOD AND APPARATUS FOR HARDWARE XML ACCELERATION
    4.
    发明申请
    METHOD AND APPARATUS FOR HARDWARE XML ACCELERATION 审中-公开
    用于硬件XML加速的方法和设备

    公开(公告)号：WO2007058949A2

    公开(公告)日：2007-05-24

    申请号：PCT/US2006/043811

    申请日：2006-11-08

    Applicant: SUN MICROSYSTEMS, INC. ,  BEHRENS, Jochen ,  DIGNUM, Marcelino M. ,  SELTZER, Wayne F. ,  ZAUMEN, William T. ,  PETRY, John P. ,  PERICAS-GEERTSEN, Santiago M. ,  NAG, Biswadeep

    Inventor： BEHRENS, Jochen ,  DIGNUM, Marcelino M. ,  SELTZER, Wayne F. ,  ZAUMEN, William T. ,  PETRY, John P. ,  PERICAS-GEERTSEN, Santiago M. ,  NAG, Biswadeep

    CPC classification number: G06F15/7842

    Abstract: A method and apparatus for accelerating processing of a structured document. A hardware XML accelerator includes one or more processors (e.g., CMT processors), hardware XML parser units, cryptographic units, and various interfaces (e.g., to memory, a network, a communication bus). An XML document may be processed in its entirety or parsed in segments (e.g., as it is received). A parser unit parses a document (or segment) character by character, validates the characters, assembles tokens, extracts data, generates token headers (to describe tokens and data) and forwards the token headers and data for consumption by an application. A cryptographic unit may enforce web security, XML security or some other security scheme, by providing encryption/decryption functionality, computing digital signatures, etc. Software processing, bus utilization and latencies (e.g., memory, bus) are greatly reduced, thereby providing significantly improved XML processing and security processing throughput.

    Abstract translation: 用于加速结构化文档的处理的方法和设备。 硬件XML加速器包括一个或多个处理器（例如，CMT处理器），硬件XML解析器单元，密码单元和各种接口（例如存储器，网络，通信总线）。 XML文档可以全部处理或分段解析（例如，当它被接收时）。 解析器单元逐字符解析文档（或段），验证字符，组合令牌，提取数据，生成令牌头（用于描述令牌和数据）并转发令牌头和数据供应用程序使用。 通过提供加密/解密功能，计算数字签名等，密码单元可以实施网络安全性，XML安全性或某种其他安全性方案。软件处理，总线利用率和等待时间（例如，存储器，总线）大大减少，从而显着提供 改进了XML处理和安全处理吞吐量。

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