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    MULTI-LEVEL MEMORY WITH DIRECT ACCESS
    1.
    发明申请
    MULTI-LEVEL MEMORY WITH DIRECT ACCESS 审中-公开
    具有直接访问的多级记忆

    公开(公告)号：WO2013101050A1

    公开(公告)日：2013-07-04

    申请号：PCT/US2011/067824

    申请日：2011-12-29

    Applicant: INTEL CORPORATION ,  FANNING, Blaise ,  QAWAMI, Shekoufeh ,  TETRICK, Raymond S. ,  HADY, Frank T.

    Inventor： FANNING, Blaise ,  QAWAMI, Shekoufeh ,  TETRICK, Raymond S. ,  HADY, Frank T.

    IPC: G06F12/00 ,  G11C13/02 ,  G11C16/00

    CPC classification number: G06F3/0644 ,  G06F3/0604 ,  G06F3/0631 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/023 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/08 ,  G06F12/10 ,  G06F12/1009 ,  G06F2212/2024 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7204 ,  G11C7/1006 ,  G11C11/56 ,  G11C16/00 ,  Y02D10/13

    Abstract: Embodiments of a method, device, and system for implementing multi-level memory with direct access are disclosed. In one embodiment, the method includes designating an amount of a non-volatile random access memory (NVRAM) in a computer system to be utilized as a memory alternative for a dynamic random access memory (DRAM). The method continues by designating a second amount of the NVRAM to be utilized as a storage alternative for a mass storage device. Then the method re-designates at least a first portion of the first amount of NVRAM from the memory alternative designation to the storage alternative designation during operation of the computer system. Finally, the method re-designates at least a first portion of the second amount of NVRAM from the storage alternative designation to the memory alternative designation during operation of the computer system.

    Abstract translation: 公开了用于实现具有直接访问的多级存储器的方法，设备和系统的实施例。 在一个实施例中，该方法包括指定要用作动态随机存取存储器（DRAM）的存储器备选方案的计算机系统中的非易失性随机存取存储器（NVRAM）的量。 该方法通过指定要用作大容量存储设备的存储备用的第二数量的NVRAM来继续。 然后，该方法在计算机系统的操作期间将存储器备选指定中的第一数量的NVRAM的至少第一部分重新指定为存储备选指定。 最后，该方法在计算机系统的操作期间将第二数量的NVRAM的至少第一部分从存储替代指定重新指定到存储器备选指定。

    COMMAND-BASED CONTROL OF NAND FLASH MEMORY
    2.
    发明申请
    COMMAND-BASED CONTROL OF NAND FLASH MEMORY 审中-公开
    NAND FLASH存储器的基于命令的控制

    公开(公告)号：WO2008079788A1

    公开(公告)日：2008-07-03

    申请号：PCT/US2007/087811

    申请日：2007-12-17

    Applicant: INTEL CORPORATION ,  ROZMAN, Rodney ,  EILERT, Sean ,  QAWAMI, Shekoufeh

    Inventor： ROZMAN, Rodney ,  EILERT, Sean ,  QAWAMI, Shekoufeh

    IPC: G06F12/00 ,  G11C16/02

    CPC classification number: G11C16/10

    Abstract: Some embodiments of the invention use a command-based interface to control reads and writes with non-volatile memory devices. This may reduce the number of pins that are needed on each integrated circuit, and therefore reduce the cost and size of those integrated circuits. In some embodiments, an on-die cache buffer may be used to buffer data transfers between a high-speed memory bus and the slower speed non-volatile array.

    Abstract translation: 本发明的一些实施例使用基于命令的接口来控制具有非易失性存储器设备的读取和写入。 这可能减少每个集成电路所需的引脚数，从而降低这些集成电路的成本和尺寸。 在一些实施例中，片上高速缓冲存储器可用于缓冲高速存储器总线与较慢速度非易失性阵列之间的数据传输。

    PHASE CHANGE MEMORY WITH SWITCH (PCMS) WRITE ERROR DETECTION
    5.
    发明申请
    PHASE CHANGE MEMORY WITH SWITCH (PCMS) WRITE ERROR DETECTION 审中-公开
    相位变化记忆与开关（PCMS）写入错误检测

    公开(公告)号：WO2013101196A1

    公开(公告)日：2013-07-04

    申请号：PCT/US2011/068139

    申请日：2011-12-30

    Applicant: INTEL CORPORATION ,  QAWAMI, Shekoufeh ,  SUNDARAM, Rajesh

    Inventor： QAWAMI, Shekoufeh ,  SUNDARAM, Rajesh

    IPC: G11C29/00 ,  G11C13/02 ,  G06F11/16

    CPC classification number: G06F11/1048 ,  G06F11/073 ,  G06F11/0763 ,  G06F11/1068 ,  G11C13/0004

    Abstract: Methods and apparatus related to PCMS (Phase Change Memory with Switch) write error detection are described. In one embodiment, a first storage unit stores a single bit to indicate whether an error corresponding to a write operation in any of one or more PCMS devices has occurred. Also, one or more storage units each store a plurality of bits to indicate whether the error corresponding to the write operation has occurred in a partition of a plurality of partitions of the one or more PCMS devices. Other embodiments are also disclosed and claimed.

    Abstract translation: 描述了与PCMS（带切换的相变存储器）写入错误检测相关的方法和装置。 在一个实施例中，第一存储单元存储单个位以指示是否发生了与一个或多个PCMS设备中的任一个中的写入操作相对应的错误。 此外，一个或多个存储单元每个存储多个位以指示与一个或多个PCMS设备的多个分区的分区中是否发生了与写入操作相对应的错误。 还公开并要求保护其他实施例。

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