公开(公告)号：WO2007116275A1

公开(公告)日：2007-10-18

申请号：PCT/IB2007/000822

申请日：2007-03-27

Applicant: MARVELL WORLD TRADE LTD. ,  RAMAMOORTHY, Aditya

Inventor： RAMAMOORTHY, Aditya

IPC: H03M13/25 ,  H03M13/11

CPC classification number: H03M13/255 ,  G06F11/1072 ,  G11C11/5621 ,  H03M13/11

Abstract: Embodiments of the present invention provide a memory apparatus that includes a memory block comprising a plurality of memory cells, each memory cell adapted to operate with multi-level signals. Such a memory apparatus also includes a low density parity check (LDPC) coder (600) to LDPC code data values to be written into the memory cells and an interleaver (602) and a mapper (604) adapted to apply bit interleaved code modulation (BICM) to the LDPC coded data values to generate BICM coded data values.

Abstract translation: 本发明的实施例提供了一种存储装置，其包括包括多个存储单元的存储块，每个存储单元适于用多电平信号进行操作。 这样一种存储装置还包括：将要写入存储单元的数据值进行LDPC编码的低密度奇偶校验（LDPC）编码器（600），以及适用于应用位交织代码调制的交织器（602）和映射器（604） BICM）到LDPC编码数据值以生成BICM编码数据值。

公开(公告)号：WO2007084749A3

公开(公告)日：2008-04-10

申请号：PCT/US2007001620

申请日：2007-01-19

Applicant: MARVELL WORLD TRADE LTD ,  RAMAMOORTHY ADITYA ,  WU ZINING ,  SUTARDJA PANTAS

Inventor： RAMAMOORTHY ADITYA ,  WU ZINING ,  SUTARDJA PANTAS

IPC: G11C11/34 ,  G11C16/04

CPC classification number: G06F11/1068 ,  G06F11/1072 ,  G06F11/1666 ,  G06F2212/403 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/56 ,  G11C11/5621 ,  G11C16/10 ,  G11C27/005 ,  G11C29/00 ,  G11C2029/0411 ,  G11C2207/16 ,  G11C2211/562 ,  G11C2211/563 ,  H03M13/1177 ,  H03M13/1515

Abstract: A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.

Abstract translation: 固态非易失性存储器单元。 存储单元包括适于存储以第一数量级数字表征的数据的多级固态非易失性存储器阵列。 存储器单元还包括具有输入和输出的模拟 - 数字转换器。 模拟 - 数字转换器的输入适于从多级固态非易失性存储器阵列接收数据。 模拟 - 数字转换器的输出适于输出特征在于数字电平大于第一数字电平数量的第二数字电平的数字信号。

公开(公告)号：WO2007084749A2

公开(公告)日：2007-07-26

申请号：PCT/US2007/001620

申请日：2007-01-19

Applicant: MARVELL WORLD TRADE LTD. ,  RAMAMOORTHY, Aditya ,  WU, Zining ,  SUTARDJA, Pantas

Inventor： RAMAMOORTHY, Aditya ,  WU, Zining ,  SUTARDJA, Pantas

IPC: G11C16/04

CPC classification number: G06F11/1068 ,  G06F11/1072 ,  G06F11/1666 ,  G06F2212/403 ,  G11C7/02 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/56 ,  G11C11/5621 ,  G11C16/10 ,  G11C27/005 ,  G11C29/00 ,  G11C2029/0411 ,  G11C2207/16 ,  G11C2211/562 ,  G11C2211/563 ,  H03M13/1177 ,  H03M13/1515

Abstract: A solid state non-volatile memory unit. The memory unit includes a multi-level solid state non-volatile memory array adapted to store data characterized by a first number of digital levels. The memory unit also includes an analog-to-digital converter having an input and an output. The input of the analog-to-digital converter is adapted to receive data from the multi-level solid state non-volatile memory array. The output of the analog-to-digital converter is adapted to output a digital signal characterized by a second number of digital levels greater than the first number of digital levels.

Abstract translation: 固态非易失性存储器单元。 存储单元包括适于存储以第一数量级数字表征的数据的多级固态非易失性存储器阵列。 存储器单元还包括具有输入和输出的模拟 - 数字转换器。 模拟 - 数字转换器的输入适于从多级固态非易失性存储器阵列接收数据。 模拟 - 数字转换器的输出适于输出特征在于数字电平大于第一数字电平数量的第二数字电平的数字信号。