公开(公告)号：WO2012119148A1

公开(公告)日：2012-09-07

申请号：PCT/US2012/027739

申请日：2012-03-05

Applicant: QUALCOMM INCORPORATED ,  RYCHLIK, Bohuslav ,  SARTORIUS, Thomas Andrew ,  MORROW, Michael William ,  PALMA, Raymond P.

Inventor： RYCHLIK, Bohuslav ,  SARTORIUS, Thomas Andrew ,  MORROW, Michael William ,  PALMA, Raymond P.

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/6026 ,  G06F2212/6028 ,  G06F2212/654

Abstract: Systems and method for memory management units (MMUs) configured to automatically pre-fill a translation lookaside buffer (TLB) (206, 208) with address translation (202-204) entries expected to be used in the future, thereby reducing TLB miss rate and improving performance. The TLB may be pre-filled with translation entries, wherein addresses corresponding to the pre-fill may be selected based on predictions. Predictions may be derived from external devices (214), or based on stride values, wherein the stride values may be a predetermined constant or dynamically altered based on access patterns (216). Pre-filling the TLB may effectively remove latency involved in determining address translations for TLB misses from the critical path.

Abstract translation: 用于存储器管理单元（MMU）的系统和方法，被配置为使用预期在将来使用的地址转换（202-204）的条目自动预填充翻译后备缓冲器（206,208），从而减少TLB未命中率 并提高性能。 可以预先填充TLB，其中可以基于预测来选择与预填充相对应的地址。 可以从外部设备（214）或基于步幅值导出预测，其中步幅值可以是预定常数或基于访问模式（216）动态地改变。 预填充TLB可以有效地消除从关键路径确定TLB未命中的地址转换所涉及的延迟。

公开(公告)号：WO2008124473A1

公开(公告)日：2008-10-16

申请号：PCT/US2008/059222

申请日：2008-04-03

Applicant: QUALCOMM Incorporated ,  STEMPEL, Brian, Michael ,  SARTORIUS, Thomas, Andrew ,  SMITH, Rodney, Wayne

Inventor： STEMPEL, Brian, Michael ,  SARTORIUS, Thomas, Andrew ,  SMITH, Rodney, Wayne

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30047 ,  G06F9/30152 ,  G06F9/3802 ,  G06F9/382

Abstract: In a processor executing instructions from a variable-length instruction set, a preload instruction is operative to retrieve from memory a data block corresponding to an instruction cache line, pre-decode instructions from a variable-length instruction set in the data block, and load the instructions and pre-decode information into the instruction cache. An instruction execution unit indicates to a pre-decoder the position within the data block of a first valid instruction. The pre-decoder successively determines the length of each instruction and hence the instruction boundaries. An instruction cache line offset indicator that identifies the position of the first valid instruction may be generated and provided to the pre-decoder in a variety of ways.

Abstract translation: 在执行来自可变长度指令集的指令的处理器中，预加载指令用于从存储器检索与指令高速缓存行相对应的数据块，对来自数据块中的可变长度指令集的指令进行预解码，以及负载 指令和预解码信息到指令缓存中。 指令执行单元向预解码器指示第一有效指令的数据块内的位置。 预解码器依次确定每个指令的长度，从而确定指令边界。 可以以各种方式生成识别第一有效指令的位置的指令高速缓存行偏移指示符并将其提供给预解码器。

公开(公告)号：WO2008021763A1

公开(公告)日：2008-02-21

申请号：PCT/US2007/075194

申请日：2007-08-03

Applicant: QUALCOMM INCORPORATED ,  BURKE, Kevin, Charles ,  STEMPEL, Brian, Michael ,  STREETT, Daren, Eugene ,  SAPP, Kevin, Allen ,  DEBRUYNE, Leslie, Mark ,  RIZK, Nabil, Amir ,  SARTORIUS, Thomas, Andrew ,  SMITH, Rodney, Wayne

Inventor： BURKE, Kevin, Charles ,  STEMPEL, Brian, Michael ,  STREETT, Daren, Eugene ,  SAPP, Kevin, Allen ,  DEBRUYNE, Leslie, Mark ,  RIZK, Nabil, Amir ,  SARTORIUS, Thomas, Andrew ,  SMITH, Rodney, Wayne

IPC: G06F11/36

CPC classification number: G06F11/3648

Abstract: A processor is operative to execute two or more instruction sets, each in a different instruction set operating mode. As each instruction is executed, debug circuit comparison the current instruction set operating mode to a target instruction set operating mode sent by a programmer, and outputs an alert or indication in they match. The alert or indication may additionally be dependent upon the instruction address following within a predetermined target address range. The alert or indication may comprise a breakpoint signal that halts execution and/or it is output as an external signal of the processor. The instruction address at which the processor detects a match in the instruction set operating modes may additionally be output. Additionally or alternatively, the alert or indication may comprise starting or stopping a trace operation, causing an exception, or any other known debugger function.

Abstract translation: 处理器可操作以执行两个或更多个指令集，每个指令集在不同的指令集操作模式中。 当执行每个指令时，调试电路将当前指令集操作模式与编程器发送的目标指令集操作模式进行比较，并输出其中的警报或指示。 警报或指示还可以依赖于在预定目标地址范围内的指令地址。 警报或指示可以包括停止执行的断点信号和/或其作为处理器的外部信号输出。 可以另外输出处理器在指令集操作模式中检测到匹配的指令地址。 附加地或替代地，警报或指示可以包括启动或停止跟踪操作，引起异常或任何其他已知的调试器功能。

公开(公告)号：WO2008014287A1

公开(公告)日：2008-01-31

申请号：PCT/US2007/074263

申请日：2007-07-24

Applicant: QUALCOMM INCORPORATED ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne ,  MCILVAINE, Michael Scott

Inventor： SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne ,  MCILVAINE, Michael Scott

IPC: G06F9/32 ,  G06F9/38 ,  G06F9/42 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/30054 ,  G06F9/3017 ,  G06F9/30181 ,  G06F9/3836

Abstract: A system, apparatus and method for efficiently processing interrupts using general purpose registers in a pipelined processor. In accordance with the present disclosure, a register file may be updated to efficiently save an interrupt return address. When an interrupt request is received by the system's processor, or when the request is issued in the execution of a program, a pseudo-instruction is generated. This pseudo-instruction travels down the pipeline in the same way as other instructions and updates the register file by causing the register file to be written with the return address of the last instruction for which processing has not been completed.

Abstract translation: 一种用于在流水线处理器中使用通用寄存器来有效地处理中断的系统，装置和方法。 根据本公开，可以更新寄存器文件以有效地保存中断返回地址。 当系统的处理器接收到中断请求时，或者当执行程序发出请求时，产生伪指令。 该伪指令以与其他指令相同的方式沿着流水线行进，并通过使用寄存器文件写入尚未完成处理的最后一条指令的返回地址来更新寄存器文件。

公开(公告)号：WO2007124307A2

公开(公告)日：2007-11-01

申请号：PCT/US2007/066802

申请日：2007-04-17

Applicant: QUALCOMM INCORPORATED ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne ,  STREETT, Daren Eugene

Inventor： SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne ,  STREETT, Daren Eugene

CPC classification number: G06F12/1063 ,  G06F12/0891 ,  G06F2212/1056 ,  G06F2212/683

Abstract: An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.

Abstract translation: 公开了一种具有虚拟标记的指令高速缓存的指令高速缓存系统，从软件程序角度来看，其操作就好像它是物理标记的指令高速缓存。 指令高速缓存系统还包括用于地址转换的装置，它响应地址转换无效指令和控制逻辑电路。 控制逻辑电路被配置为响应于地址转换无效指令使虚拟标记的指令高速缓存中的条目无效。

公开(公告)号：WO2006124410A3

公开(公告)日：2007-09-20

申请号：PCT/US2006017899

申请日：2006-05-08

Applicant: QUALCOMM INC ,  DOCKSER KENNETH ALAN ,  AUGSBURG VICTOR ROBERTS ,  DIEFFENDERFER JAMES NORRIS ,  BRIDGES JEFFREY TODD ,  CLANCY ROBERT DOUGLAS ,  SARTORIUS THOMAS ANDREW

Inventor： DOCKSER KENNETH ALAN ,  AUGSBURG VICTOR ROBERTS ,  DIEFFENDERFER JAMES NORRIS ,  BRIDGES JEFFREY TODD ,  CLANCY ROBERT DOUGLAS ,  SARTORIUS THOMAS ANDREW

IPC: G06F13/38

CPC classification number: G06F13/4059 ,  G06F5/06 ,  G06F2205/126

Abstract: Data from a source domain (311 ) operating at a first data rate is transferred to a FIFO (319) in another domain (313) operating at a different data rate. The FIFO (319) buffers data before transfer to a sink for further processing or storage. A source side counter (325) tracks space available in the FIFO. In disclosed examples, the initial counter value corresponds to FIFO depth. The counter (325) decrements in response to a data ready signal from the source domain (311)1 without delay. The counter (325) increments in response to signaling from the sink domain (313) of a read of data off the FIFO (319). Hence, incrementing is subject to the signaling latency between domains. The source (315) may send one more beat of data when the counter (325) indicates the FIFO (319) is full. The last beat of data is continuously sent from the source until it is indicated that a FIFO position became available; effectively providing one o more FIFO positions.

Abstract translation: 来自以第一数据速率运行的源域（311）的数据被传送到以不同数据速率工作的另一域（313）中的FIFO（319）。 FIFO（319）在传输到宿之前缓冲数据以进一步处理或存储。 源侧计数器（325）跟踪FIFO中可用的空间。 在所公开的示例中，初始计数器值对应于FIFO深度。 计数器（325）响应于来自源域（311）1的数据就绪信号而没有延迟地递减。 计数器（325）响应于来自接收器域（313）的从FIFO（319）读取的数据的信令而递增。 因此，增量受到域之间的信令等待时间的限制。 当计数器（325）指示FIFO（319）已满时，源（315）可以再发送一个数据节拍。 数据的最后一次节拍从源头连续发送到指示FIFO位置可用为止; 有效提供一个以上的FIFO位置。

公开(公告)号：WO2007101139A1

公开(公告)日：2007-09-07

申请号：PCT/US2007/062768

申请日：2007-02-23

Applicant: QUALCOMM INCORPORATED ,  BIRENBACH, Michael Egnoah ,  BROOKSHIRE, Gregory Lee ,  DIEFFENDERFER, James Norris ,  GEIST, Stephen, G. ,  MOORE, Richard Alan ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne

Inventor： BIRENBACH, Michael Egnoah ,  BROOKSHIRE, Gregory Lee ,  DIEFFENDERFER, James Norris ,  GEIST, Stephen, G. ,  MOORE, Richard Alan ,  SARTORIUS, Thomas Andrew ,  SMITH, Rodney Wayne

IPC: G06F9/48

CPC classification number: G06F9/4812

Abstract: A processor provides two-level interrupt servicing. In one embodiment, the processor comprises a storage device and an interrupt handler. The storage device is configured to store an interrupt identifier corresponding to an interrupt request. The interrupt handler is configured to recognize the interrupt request, initiate a common interrupt service routine responsive to recognizing the interrupt request and subsequently initiate an interrupt service routine corresponding to the stored interrupt identifier.

Abstract translation: 处理器提供两级中断服务。 在一个实施例中，处理器包括存储设备和中断处理程序。 存储装置被配置为存储对应于中断请求的中断标识符。 中断处理程序被配置为识别中断请求，响应于识别中断请求而启动公共中断服务程序，并随后发起与所存储的中断标识符相对应的中断服务程序。

公开(公告)号：WO2006135590A3

公开(公告)日：2007-05-31

申请号：PCT/US2006021617

申请日：2006-06-02

Applicant: QUALCOMM INC ,  MCILVAINE MICHAEL SCOTT ,  DIEFFENDERFER JAMES NORRIS ,  SARTORIUS THOMAS ANDREW

Inventor： MCILVAINE MICHAEL SCOTT ,  DIEFFENDERFER JAMES NORRIS ,  SARTORIUS THOMAS ANDREW

IPC: G06F9/44

CPC classification number: G06F9/3861 ,  G06F9/30072 ,  G06F9/3867 ,  G06F12/0855 ,  G06F12/0862 ,  G06F2212/6028

Abstract: In one or more embodiments, a processor includes one or more circuits to flush instructions from an instruction pipeline on a selective basis responsive to detecting a branch misprediction, such that those instructions marked as being dependent on the branch instruction associated with the branch misprediction are flushed. Thus, the one or more circuits may be configured to mark instructions fetched into the processor's instruction pipeline(s) to indicate their branch prediction dependencies, directly or indirectly detect incorrect branch predictions, and directly or indirectly flush instructions in the instruction pipeline(s) that are marked as being dependent on an incorrect branch prediction.

Abstract translation: 在一个或多个实施例中，处理器包括一个或多个电路，用于响应于检测到分支错误预测而选择性地从指令流水线中刷新指令，使得标记为依赖于与分支错误预测相关联的分支指令的那些指令被刷新 。 因此，一个或多个电路可以被配置为标记被提取到处理器的指令流水线中以指示其分支预测依赖性的指令，直接或间接地检测不正确的分支预测，以及直接或间接地刷新指令流水线中的指令， 这被标记为依赖于不正确的分支预测。

公开(公告)号：WO2007048136A3

公开(公告)日：2007-04-26

申请号：PCT/US2006/060136

申请日：2006-10-20

Applicant: QUALCOMM INCORPORATED ,  SPEIER, Thomas Philip ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew ,  GANASAN, Jaya Prakash Subramaniam

Inventor： SPEIER, Thomas Philip ,  DIEFFENDERFER, James Norris ,  SARTORIUS, Thomas Andrew ,  GANASAN, Jaya Prakash Subramaniam

IPC: G06F9/46

Abstract: Semaphore (116) operation manages exclusive access to a memory (114) that is shared by a plurality of processing elements. Semaphore reservation status for exclusive access by a processing element is (102a), (102b) monitored by a memory controller. To clear an obsolete reservation status, a command signal is transmitted for a write operation to the memory while prohibiting update of the contents of a memory. The reservation status at the controller (104) is changed from a reservation state to a non-reservation state in response to receipt of the command signal.

公开(公告)号：WO2006089194A3

公开(公告)日：2007-03-29

申请号：PCT/US2006005782

申请日：2006-02-16

Applicant: QUALCOMM INC ,  BRIDGES JEFFREY TODD ,  AUGSBURG VICTOR ROBERTS ,  DIEFFENDERFER JAMES NORRIS ,  SARTORIUS THOMAS ANDREW

Inventor： BRIDGES JEFFREY TODD ,  AUGSBURG VICTOR ROBERTS ,  DIEFFENDERFER JAMES NORRIS ,  SARTORIUS THOMAS ANDREW

IPC: G06F9/312 ,  G06F9/318 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/30145 ,  G06F9/30189 ,  G06F9/3824 ,  G06F9/3832 ,  G06F9/3855

Abstract: In an instruction execution pipeline, the misalignment of memory access instructions is predicted. Based on the prediction, an additional micro-operation is generated in the pipeline prior to the effective address generation of the memory access instruction. The additional micro-operation accesses the memory falling across a predetermined address boundary. Predicting the misalignment and generating a micro-operation early in the pipeline ensures that sufficient pipeline control resources are available to generate and track the additional micro-operation, avoiding a pipeline flush if the resources are not available at the time of effective address generation. The misalignment prediction may employ known conditional branch prediction techniques, such as a flag, a bimodal counter, a local predictor, a global predictor, and combined predictors. A misalignment predictor may be enabled or biased by a memory access instruction flag or misaligned instruction type.

Abstract translation: 在指令执行流水线中，预测存储器访问指令的未对准。 基于该预测，在存储器访问指令的有效地址生成之前在流水线中生成附加的微操作。 附加的微操作访问落在预定地址边界上的存储器。 预测未对准并在管道早期生成微操作确保足够的流水线控制资源可用于生成和跟踪额外的微操作，如果资源在有效地址生成时不可用，则避免管道冲洗。 不对准预测可以使用已知的条件分支预测技术，例如标志，双模计数器，局部预测器，全局预测器和组合预测器。 未对准预测器可能被存储器访问指令标志或未对准指令类型使能或偏置。