公开(公告)号：WO2011041612A1

公开(公告)日：2011-04-07

申请号：PCT/US2010/051007

申请日：2010-09-30

Applicant: QUALCOMM INCORPORATED ,  SEO, Dongwon ,  SARIPALLI, Ganesh ,  SONG, Tongyu ,  TALEIE, Shahin, Mehdizad ,  KONG, Derui

Inventor： SEO, Dongwon ,  SARIPALLI, Ganesh ,  SONG, Tongyu ,  TALEIE, Shahin, Mehdizad ,  KONG, Derui

IPC: H03M1/74

CPC classification number: H03M1/742 ,  H03F1/223 ,  H03F1/3241 ,  H03F3/195 ,  H03F3/245 ,  H03F3/45183

Abstract: A circuit for digital-to-analog conversion is described. The circuit includes a digital-to-analog converter (DAC). The DAC includes a double cascaded current source and a differential current-mode switch (DCMS). The circuit further includes a direct current (DC) offset stage. The circuit also includes a load attenuator. The double cascaded current source may be between the DCMS and a rail voltage.

Abstract translation: 描述用于数模转换的电路。 该电路包括一个数模转换器（DAC）。 DAC包括双级联电流源和差分电流模式开关（DCMS）。 电路还包括直流（DC）偏置级。 该电路还包括负载衰减器。 双级联电流源可以在DCMS和导轨电压之间。

公开(公告)号：WO2010115152A1

公开(公告)日：2010-10-07

申请号：PCT/US2010/029850

申请日：2010-04-02

Applicant: QUALCOMM INCORPORATED ,  QUAN, Xiaohong ,  SONG, Tongyu ,  MATHE, Lennart ,  ALLADI, Dinesh, J.

Inventor： QUAN, Xiaohong ,  SONG, Tongyu ,  MATHE, Lennart ,  ALLADI, Dinesh, J.

IPC: H03L7/08 ,  H03K3/017 ,  H03M1/12

CPC classification number: H03L7/0812 ,  H03K5/1515 ,  H03K5/1565 ,  H03K2005/00039 ,  H03K2005/00097 ,  H03K2005/00286 ,  H03M1/12

Abstract: Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non- overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non- overlapping time (tnlp) that is independent of manufacturing process variations.

Abstract translation: 提供了用于在所需频率范围内产生精确的非重叠时间和时钟相位延迟时间的技术。 在一种配置中，设备包括不重叠的时钟产生电路，其包括延迟锁定环（DLL）电路，该延迟锁定环路（DLL）电路又向与其耦合的时钟发生器电路产生控制电压。 控制电压操作以保持由时钟发生器电路产生的非重叠延迟时钟信号的精确定时关系。 在一个方面，DLL电路接收具有已知占空比的输入时钟，并且导出输出控制电压以将单位延迟固定到输入时钟周期的某一部分。 在另一方面，时钟发生器电路包括耦合到DLL电路的多个电压控制延迟单元，以产生第一组时钟信号和从第一组时钟信号延迟的第二组时钟信号， 重叠时间（tnlp），与制造过程变化无关。