公开(公告)号：WO2010141908A1

公开(公告)日：2010-12-09

申请号：PCT/US2010/037528

申请日：2010-06-04

Applicant: QUALCOMM INCORPORATED ,  TASIC, Aleksandar M. ,  CASSIA, Marco

Inventor： TASIC, Aleksandar M. ,  CASSIA, Marco

IPC: H03F3/193 ,  H04B1/40

CPC classification number: H04B1/406 ,  H03F3/195 ,  H03F3/45179 ,  H03F3/45475 ,  H03F3/72 ,  H03F2203/45386 ,  H03F2203/45394 ,  H03F2203/7209

Abstract: A device with multiple multi-mode low-noise amplifiers (LNAs), each with common operating modes and separate operating frequency bands, are coupled to shared degenerative inductors for common operating modes. Common load inductors are coupled to the multi-mode LNA outputs to reduce the number of load inductors required. The multi-mode LNAs have parallel transistor gain stages and form part of an integrated circuit (IC) for use in a wireless communication receiver. Each multi-mode LNA has the capability to switch between at least one higher linearity transistor gain stage and at least one lower linearity transistor gain stage for different operating modes. Multiple lower linearity transistor gain stages for different multi-mode LNAs may be merged into a single lower linearity transistor gain stage shared among multiple multi-mode LNAs through multiple RF switches between a set of common RF inputs and common inputs and common input matching networks.

Abstract translation: 具有多个多模低噪声放大器（LNA）的器件，每个具有共同的工作模式和独立的工作频带，耦合到用于常见工作模式的共享退化电感器。 常见的负载电感器耦合到多模LNA输出，以减少所需的负载电感器的数量。 多模LNA具有并联晶体管增益级并且构成用于无线通信接收机的集成电路（IC）的一部分。 每个多模式LNA具有在至少一个较高线性度晶体管增益级与用于不同操作模式的至少一个较低线性度晶体管增益级之间切换的能力。 用于不同多模LNA的多个下线性晶体管增益级可以通过一组公共RF输入和公共输入和公共输入匹配网络之间的多个RF开关合并到多个多模LNA之间共享的单个下线性晶体管增益级中。

公开(公告)号：WO2010132699A1

公开(公告)日：2010-11-18

申请号：PCT/US2010/034784

申请日：2010-05-13

Applicant: QUALCOMM INCORPORATED ,  CASSIA, Marco ,  TASIC, Aleksandar M.

Inventor： CASSIA, Marco ,  TASIC, Aleksandar M.

IPC: H03F3/21 ,  H03F3/45 ,  H03F3/72 ,  H03F3/19 ,  H03G1/00

CPC classification number: H03F3/72 ,  H03F3/19 ,  H03F3/211 ,  H03F3/45183 ,  H03F2200/111 ,  H03F2200/294 ,  H03F2200/429 ,  H03F2200/451 ,  H03F2203/21136 ,  H03F2203/21178 ,  H03F2203/45318 ,  H03F2203/45352 ,  H03F2203/45616 ,  H03F2203/45702 ,  H03F2203/7209 ,  H03F2203/7215 ,  H03F2203/7236 ,  H03F2203/7239

Abstract: Techniques for designing a switchable amplifier are described. In one aspect, a switchable amplifier including a core amplifier circuit configured to selectively enable one or more parallel input transistor pairs is described. The core amplifier circuit comprises a permanently enabled input transistor pair. In another aspect, a device operable between a first mode of operation and a second mode of operation comprising a receiver logic circuit for selectably enabling and disabling a plurality of input transistor pairs within a switchable amplifier is described where the switchable amplifier also includes a core amplifier circuit coupled to the receiver logic circuit for selectably enabling and disabling a transistor pair therein. The described switchable amplifiers result in the ability to provide varying amplifier performance characteristics based upon the current mode of operation of the device.

Abstract translation: 描述了用于设计可切换放大器的技术。 在一个方面，描述了一种可切换放大器，其包括被配置为选择性地启用一个或多个并行输入晶体管对的核心放大器电路。 核心放大器电路包括永久使能的输入晶体管对。 在另一方面，描述了在第一操作模式和第二操作模式之间操作的装置，其包括用于可切换地启用和禁用可切换放大器内的多个输入晶体管对的接收器逻辑电路，其中可切换放大器还包括芯放大器 耦合到接收器逻辑电路的电路，用于可选地启用和禁用其中的晶体管对。 所描述的可切换放大器导致基于设备的当前操作模式来提供变化的放大器性能特征的能力。

公开(公告)号：WO2011068913A1

公开(公告)日：2011-06-09

申请号：PCT/US2010/058619

申请日：2010-12-01

Applicant: QUALCOMM INCORPORATED ,  JIN, Zhang ,  HADJICHRISTOS, Aristotele ,  LEE, Ockgoo ,  YAN, Hongyan ,  KLEMENS, Guy ,  BHAGAT, Maulin, P. ,  MYERS, Thomas ,  FREDERICK, Norman, L. ,  DENG, Junxiong ,  TASIC, Aleksandar ,  ASURI, Bhushan, S. ,  FARAZIAN, Mohammad

Inventor： JIN, Zhang ,  HADJICHRISTOS, Aristotele ,  LEE, Ockgoo ,  YAN, Hongyan ,  KLEMENS, Guy ,  BHAGAT, Maulin, P. ,  MYERS, Thomas ,  FREDERICK, Norman, L. ,  DENG, Junxiong ,  TASIC, Aleksandar ,  ASURI, Bhushan, S. ,  FARAZIAN, Mohammad

IPC: H01L25/16 ,  H01L23/64

CPC classification number: H01L25/16 ,  H01F17/0006 ,  H01F27/40 ,  H01L23/645 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit is described. The integrated circuit includes an inductor that has a large empty area in the center of the inductor. The integrated circuit also includes additional circuitry. The additional circuitry is located within the large empty area in the center of the inductor. The additional circuitry may include a capacitor bank, transistors, electrostatic discharge (ESD) protection circuitry and other miscellaneous passive or active circuits.

Abstract translation: 描述了集成电路。 集成电路包括在电感器中心具有大的空白区域的电感器。 集成电路还包括附加电路。 附加电路位于电感器中心的大空区域内。 附加电路可以包括电容器组，晶体管，静电放电（ESD）保护电路和其它各种无源或有源电路。

公开(公告)号：WO2011103103A1

公开(公告)日：2011-08-25

申请号：PCT/US2011/024942

申请日：2011-02-15

Applicant: QUALCOMM Incorporated ,  TASIC, Aleksandar M. ,  DENG, Junxiong ,  QIAO, Dongjiang

Inventor： TASIC, Aleksandar M. ,  DENG, Junxiong ,  QIAO, Dongjiang

IPC: H03K21/08 ,  H03K23/66

CPC classification number: H03K21/08 ,  H03K23/66 ,  H03L7/1976

Abstract: A divide-by-three circuit includes a chain of three dynamic flip-flops and a feedback circuit of combinatorial logic. The divide-by-three circuit receives a clock signal that synchronously clocks each dynamic flip-flop. The feedback circuit supplies a feedback signal onto the first dynamic-flop of the chain. In a first mode, a signal from a slave stage of the first flip-flop and a signal from a slave stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. In a second mode, a signal from a master stage of the first flip-flop and a signal from a master stage of the second flip-flop are used by the feedback circuit to generate the feedback signal. By proper selection of the mode, the frequency range of the overall divider is extended. Combinatorial logic converts thirty-three percent duty cycle signals from the flip-flop chain into fifty percent duty cycle quadrature signals.

Abstract translation: 三分之一电路包括三个动态触发器链和组合逻辑的反馈电路。 分频电路接收时钟信号，同步地对每个动态触发器进行时钟。 反馈电路将反馈信号提供给链的第一动态触发器。 在第一模式中，来自第一触发器的从动级的信号和来自第二触发器的从动级的信号由反馈电路用于产生反馈信号。 在第二模式中，来自第一触发器的主级的信号和来自第二触发器的主级的信号由反馈电路用于产生反馈信号。 通过正确选择该模式，扩展整体分频器的频率范围。 组合逻辑将三十三％的占空比信号从触发器链转换为五十％的占空比正交信号。

公开(公告)号：WO2011011754A1

公开(公告)日：2011-01-27

申请号：PCT/US2010/043153

申请日：2010-07-23

Applicant: QUALCOMM Incorporated ,  TASIC, Aleksandar ,  DENG, Junxiong ,  JIN, Zhang

Inventor： TASIC, Aleksandar ,  DENG, Junxiong ,  JIN, Zhang

IPC: H03F1/32 ,  H03F3/193 ,  H03F3/68

CPC classification number: H03F1/3205 ,  H03F1/223 ,  H03F3/193 ,  H03F3/45179 ,  H03F3/68 ,  H03F2200/492

Abstract: A multi-mode low noise amplifier (LNA) with transformer source degeneration is described. In an exemplary design, the multi-mode LNA includes first, second, and third transistors and first and second inductors. The first transistor has its source coupled to the first inductor, amplifies an input signal, and provides a first amplified signal in a first mode. The second transistor has its source coupled to the second inductor, amplifies the input signal, and provides a second amplified signal in a second mode. The third transistor has its source coupled to the second inductor. The first and third transistors receive the input signal and conduct current through the first and second inductors, respectively, in a third mode. The first transistor observes source degeneration from a transformer formed by the first and second inductors, amplifies the input signal, and provides a third amplified signal in the third mode.

Abstract translation: 描述了具有变压器源变性的多模低噪声放大器（LNA）。 在示例性设计中，多模LNA包括第一，第二和第三晶体管以及第一和第二电感器。 第一晶体管的源极耦合到第一电感器，放大输入信号，并以第一模式提供第一放大信号。 第二晶体管的源极耦合到第二电感器，放大输入信号，并以第二模式提供第二放大信号。 第三晶体管的源极耦合到第二电感器。 第一和第三晶体管以第三模式分别接收输入信号并且分别通过第一和第二电感器传导电流。 第一晶体管观察由第一和第二电感器形成的变压器的源极退化，放大输入信号，并在第三模式中提供第三放大信号。

公开(公告)号：WO2010017137A3

公开(公告)日：2010-04-01

申请号：PCT/US2009052583

申请日：2009-08-03

Applicant: QUALCOMM INC ,  TASIC ALEKSANDAR ,  HOLENSTEIN CHRISTIAN ,  DENG JUNXIONG

Inventor： TASIC ALEKSANDAR ,  HOLENSTEIN CHRISTIAN ,  DENG JUNXIONG

IPC: H03G3/30

CPC classification number: H03G3/3052

Abstract: A circuit is described. The circuit includes a low noise amplifier (LNA), a passive switching core (PSC), a transimpedance amplifier filter (TIA-filter) and a degenerative-impedance gain-tuning network (Zdeg network) having a first Zdeg network input lead, a second Zdeg network input lead, a first Zdeg network output lead and a second Zdeg network output lead, wherein the first Zdeg network input lead is coupled to a first output lead of the LNA and the second Zdeg network input lead is coupled to a second output lead of the LNA, and wherein the first Zdeg network output lead is coupled to a first signal input lead of the PSC and the second Zdeg network output lead is coupled to a second signal input lead of the PSC. The LNA, the Zdeg network, the PSC, and the TIA-filter together form a receiver. A receiver gain is adjusted by the Zdeg network.

Abstract translation: 描述了一个电路。 该电路包括具有第一Zdeg网络输入引线的低噪声放大器（LNA），无源切换核心（PSC），跨阻抗放大器滤波器（TIA滤波器）和退化阻抗增益调谐网络（Zdeg网络）， 第二Zdeg网络输入引线，第一Zdeg网络输出引线和第二Zdeg网络输出引线，其中第一Zdeg网络输入引线耦合到LNA的第一输出引线并且第二Zdeg网络输入引线耦合到第二输出引线 并且其中所述第一Zdeg网络输出引线耦合到所述PSC的第一信号输入引线，并且所述第二Zdeg网络输出引线耦合到所述PSC的第二信号输入引线。 LNA，Zdeg网络，PSC和TIA滤波器一起构成一个接收器。 接收器增益由Zdeg网络调整。

公开(公告)号：WO2010017137A2

公开(公告)日：2010-02-11

申请号：PCT/US2009/052583

申请日：2009-08-03

Applicant: QUALCOMM INCORPORATED ,  TASIC, Aleksandar ,  HOLENSTEIN, Christian ,  DENG, Junxiong

Inventor： TASIC, Aleksandar ,  HOLENSTEIN, Christian ,  DENG, Junxiong

IPC: H03G1/00 ,  H03G3/30

CPC classification number: H03G3/3052

Abstract: A circuit is described. The circuit includes a low noise amplifier (LNA), a passive switching core (PSC), a transimpedance amplifier filter (TIA-filter) and a degenerative-impedance gain-tuning network (Zdeg network) having a first Zdeg network input lead, a second Zdeg network input lead, a first Zdeg network output lead and a second Zdeg network output lead, wherein the first Zdeg network input lead is coupled to a first output lead of the LNA and the second Zdeg network input lead is coupled to a second output lead of the LNA, and wherein the first Zdeg network output lead is coupled to a first signal input lead of the PSC and the second Zdeg network output lead is coupled to a second signal input lead of the PSC. The LNA, the Zdeg network, the PSC, and the TIA-filter together form a receiver. A receiver gain is adjusted by the Zdeg network.

Abstract translation: 描述电路。 该电路包括具有第一Zdeg网络输入引线的低噪声放大器（LNA），无源开关核心（PSC），跨阻抗放大器滤波器（TIA滤波器）和退化阻抗增益调谐网络（Zdeg网络） 第二Zdeg网络输入引线，第一Zdeg网络输出引线和第二Zdeg网络输出引线，其中第一Zdeg网络输入引线耦合到LNA的第一输出引线，而第二Zdeg网络输入引线耦合到第二输出 LNA的引线，并且其中第一Zdeg网络输出引线耦合到PSC的第一信号输入引线，并且第二Zdeg网络输出引线耦合到PSC的第二信号输入引线。 LNA，Zdeg网络，PSC和TIA滤波器一起形成接收器。 接收机增益由Zdeg网络调整。

公开(公告)号：WO2009058912A1

公开(公告)日：2009-05-07

申请号：PCT/US2008/081652

申请日：2008-10-29

Applicant: QUALCOMM Incorporated ,  TASIC, Aleksandar ,  DENG, Junxiong ,  KIM, Namsoo

Inventor： TASIC, Aleksandar ,  DENG, Junxiong ,  KIM, Namsoo

IPC: H04B1/18 ,  H04B1/30

CPC classification number: H04B1/18 ,  H04B1/30

Abstract: In a SAW-less receiver involving a passive mixer, novel degenerative impedance elements having substantial impedances are disposed in incoming signal paths between the differential signal output leads of a low-noise amplifier (LNA) and the differential signal input leads of the passive mixer. The passive mixer outputs signals to a transimpedance amplifier and baseband filter (TIA). Providing the novel degenerative impedance elements decreases noise in the overall receiver as output from the TIA, with only minimal degradation of other receiver performance characteristics. In some examples, the passive mixer receives local oscillator signals having duty cycles of substantially less than fifty percent. In some examples, the degenerative impedance elements can have one of several impedances.

Abstract translation: 在涉及无源混频器的无SAW接收机中，具有实质阻抗的新型退化阻抗元件设置在低噪声放大器（LNA）的差分信号输出引线与无源混频器的差分信号输入引线之间的输入信号路径中。 无源混频器将信号输出到跨阻抗放大器和基带滤波器（TIA）。 提供新颖的退化阻抗元件降低了总体接收机中的噪声，作为TIA的输出，只有其他接收机性能特性的降低很小。 在一些示例中，无源混频器接收具有基本上小于百分之五十的占空比的本地振荡器信号。 在一些示例中，退化阻抗元件可以具有几个阻抗之一。