公开(公告)号：WO2007119389A1

公开(公告)日：2007-10-25

申请号：PCT/JP2007/055324

申请日：2007-03-12

Applicant: RICOH COMPANY, LTD. ,  UEDA, Naohiro

Inventor： UEDA, Naohiro

IPC: H01L29/78 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/088

CPC classification number: H01L29/78 ,  H01L27/088

Abstract: A disclosed semiconductor device includes a driver transistor including a source and a drain of a second conductive type provided with an interval therebetween in a semiconductor substrate of a first conductive type, a gate electrode extending in a predetermined direction and provided on the semiconductor substrate via a gate insulating film between the source and the drain, plural insular back gate diffusion layers of the first conductive type provided in the source so as to be in contact with the semiconductor substrate, wherein the back gate diffusion layers are spaced apart and arranged in the predetermined direction in the source, and a contact hole extending in the predetermined direction on the source and at least one of the back gate diffusion layers.

Abstract translation: 所公开的半导体器件包括驱动晶体管，其包括在第一导电类型的半导体衬底中设置有间隔的第二导电类型的源极和漏极，沿预定方向延伸的栅电极，并且经由 源极和漏极之间的栅极绝缘膜，设置在源极中的第一导电类型的多个岛状后栅极扩散层以与半导体衬底接触，其中后栅极扩散层间隔开并布置成预定的 在源极上的方向，以及在源极和至少一个背栅扩散层上沿预定方向延伸的接触孔。

公开(公告)号：WO2008123080A1

公开(公告)日：2008-10-16

申请号：PCT/JP2008/055015

申请日：2008-03-11

Applicant: RICOH COMPANY, LTD. ,  UEDA, Naohiro

Inventor： UEDA, Naohiro

IPC: H01L29/78 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L29/7835 ,  H01L21/823456 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/42368 ,  H01L29/66568 ,  H01L29/7831 ,  H01L29/7833 ,  H01L29/788

Abstract: ABSTRACT A disclosed semiconductor device includes a MOS transistor that causes no problems concerning the formation of a thick gate insulating film and that is applicable to high withstand voltage devices. A drain region has a double diffusion structure including an N-drain region 3d and an N+ drain region 11d. A gate electrode includes a first gate electrode 9 formed on an insulating film 7 and a second gate electrode 13 formed on the first gate electrode 9 via a gate electrode insulating film 11. Between the gate insulating film 7 and the N+ source region 11s, a field insulating film 15 is disposed, over which an edge of the first gate electrode 9 is disposed. A gate voltage applied to the second gate electrode 13 via a gate wiring 13g is divided between the gate insulating film 7 and the gate electrode insulating film 11.

Abstract translation: 摘要所公开的半导体器件包括MOS晶体管，其不会形成厚栅极绝缘膜并且适用于高耐压器件。 漏极区域具有包括N沟道区域3d和N +漏极区域11d的双扩散结构。 栅电极包括形成在绝缘膜7上的第一栅电极9和通过栅电极绝缘膜11形成在第一栅电极9上的第二栅极13.在栅绝缘膜7和N +源极区11s之间， 设置场绝缘膜15，在其上设置第一栅电极9的边缘。 通过栅极布线13g施加到第二栅电极13的栅极电压被划分在栅极绝缘膜7和栅电极绝缘膜11之间。