公开(公告)号：WO2010078167A2

公开(公告)日：2010-07-08

申请号：PCT/US2009/069286

申请日：2009-12-22

Applicant: INTEL CORPORATION ,  VOGAN, Andrew Wayne ,  COULSON, Richard

Inventor： VOGAN, Andrew Wayne ,  COULSON, Richard

IPC: G06F11/10 ,  G06F13/16

CPC classification number: G11B20/1833 ,  G06F11/1048 ,  G06F11/108 ,  G11B2220/61

Abstract: In some embodiments, a solid state disk includes a non-volatile memory and a controller. The controller performs ECC on data stored on the non-volatile memory, and performs a parity operation on the data if the ECC cannot correct the data. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，固态盘包括非易失性存储器和控制器。 控制器对存储在非易失性存储器上的数据执行ECC，并且如果ECC无法校正数据，则对数据执行奇偶校验操作。 描述和要求保护其他实施例。

公开(公告)号：WO2009020969A3

公开(公告)日：2009-04-09

申请号：PCT/US2008072227

申请日：2008-08-05

Applicant: INTEL CORP ,  VOGAN ANDREW ,  KHAN JAWAD B ,  JAYACHANDRAN SOWMIYA

Inventor： VOGAN ANDREW ,  KHAN JAWAD B ,  JAYACHANDRAN SOWMIYA

IPC: G11B20/18 ,  G06F11/10 ,  G11C29/42

CPC classification number: G11B20/18 ,  G06F11/108 ,  G11B20/10527 ,  G11B2020/1062

Abstract: A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels.

Abstract translation: 多通道存储设备可以包括主机控制器，以从主机设备和缓冲存储器接收输入数据，以在下游存储之前存储输入数据和相关联的纠错数据。 缓冲存储器下游的多个存储通道可以将输入数据和相关联的纠错数据存储在非易失性存储介质上的至少一个存储通道中。 主机控制器和缓冲存储器之间的纠错引擎可以对来自主机设备的输入数据执行纠错编码，以产生相关联的纠错数据以存储在缓冲存储器中。 这种纠错引擎可以防止缓冲存储器和存储通道中的数据错误。

公开(公告)号：WO2009020969A2

公开(公告)日：2009-02-12

申请号：PCT/US2008/072227

申请日：2008-08-05

Applicant: INTEL CORPORATION ,  VOGAN, Andrew ,  KHAN, Jawad B. ,  JAYACHANDRAN, Sowmiya

Inventor： VOGAN, Andrew ,  KHAN, Jawad B. ,  JAYACHANDRAN, Sowmiya

IPC: G11B20/18

CPC classification number: G11B20/18 ,  G06F11/108 ,  G11B20/10527 ,  G11B2020/1062

Abstract: A multiple channel storage device may include a host controller to receive input data from a host device and a buffer memory to store the input data and associated error correcting data prior to downstream storage. Multiple storage channels downstream from the buffer memory may store the input data and associated error correcting data in at least one of the storage channels on a non-volatile storage media. An error correcting engine between the host controller and the buffer memory may perform error correction encoding on the input data from the host device to generate the associated error correcting data for storage in the buffer memory. Such error correcting engine may protect against data errors in the buffer memory and in the storage channels.

Abstract translation: 多通道存储设备可以包括主机控制器，以接收来自主机设备的输入数据和缓冲存储器，以在下游存储之前存储输入数据和关联的纠错数据。 缓冲存储器下游的多个存储通道可以将输入数据和关联的纠错数据存储在非易失性存储介质上的至少一个存储通道中。 主机控制器和缓冲存储器之间的纠错引擎可以对来自主机设备的输入数据执行纠错编码，以生成关联的纠错数据以存储在缓冲存储器中。 这种纠错引擎可以防止缓冲存储器和存储通道中的数据错误。

公开(公告)号：WO2013147894A1

公开(公告)日：2013-10-03

申请号：PCT/US2012/031709

申请日：2012-03-30

Applicant: INTEL CORPORATION ,  MANGOLD, Richard P. ,  COULSON, Richard L. ,  ROYER, JR., Robert J. ,  TRIKA, Sanjeev N. ,  VOGAN, Andrew

Inventor： MANGOLD, Richard P. ,  COULSON, Richard L. ,  ROYER, JR., Robert J. ,  TRIKA, Sanjeev N. ,  VOGAN, Andrew

IPC: G11C16/34 ,  G11C16/10 ,  G06F12/00

CPC classification number: G11C16/225 ,  G06F11/1441 ,  G06F12/0246 ,  G06F2212/1032 ,  G06F2212/7205 ,  Y02D10/13

Abstract: Embodiments of the present disclosure describe devices, methods, computer-readable media and systems configurations for solid state drive management in power loss recovery. In some embodiments, an apparatus comprises non-volatile memory, and a memory controller coupled with the non-volatile memory and configured to defragment the non-volatile memory by being configured to write valid data from a first erase block into a location of a page of a second erase block, determine the valid data is associated with a secured state in the page, and erase the first erase block based on determination the valid data is associated with the secured state. Other embodiments are also disclosed and claimed.

Abstract translation: 本公开的实施例描述了在功率损耗恢复中用于固态驱动器管理的设备，方法，计算机可读介质和系统配置。 在一些实施例中，装置包括非易失性存储器，以及与非易失性存储器耦合的存储器控​​制器，并被配置为通过被配置为将有效数据从第一擦除块写入到页面的位置来对非易失性存储器进行碎片整理 确定有效数据与页面中的安全状态相关联，并且基于有效数据与安全状态相关联的确定来擦除第一擦除块。 还公开并要求保护其他实施例。

公开(公告)号：WO2010078167A3

公开(公告)日：2010-09-30

申请号：PCT/US2009069286

申请日：2009-12-22

Applicant: INTEL CORP ,  VOGAN ANDREW WAYNE ,  COULSON RICHARD

Inventor： VOGAN ANDREW WAYNE ,  COULSON RICHARD

IPC: G06F11/10 ,  G06F13/16

CPC classification number: G11B20/1833 ,  G06F11/1048 ,  G06F11/108 ,  G11B2220/61

Abstract: In some embodiments, a solid state disk includes a non-volatile memory and a controller. The controller performs ECC on data stored on the non-volatile memory, and performs a parity operation on the data if the ECC cannot correct the data. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，固态盘包括非易失性存储器和控制器。 控制器对存储在非易失性存储器上的数据执行ECC，并且如果ECC不能纠正数据，则对数据执行奇偶校验操作。 描述并要求保护其他实施例。