公开(公告)号：WO1997041640A1

公开(公告)日：1997-11-06

申请号：PCT/US1997007152

申请日：1997-04-28

Applicant: AGATE SEMICONDUCTOR, INC.

Inventor： AGATE SEMICONDUCTOR, INC. ,  KORSH, George, J. ,  KHAN, Sakhawat, M.

IPC: H03M01/00

CPC classification number: G11C11/5657 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/565 ,  G11C16/3418 ,  G11C16/3431

Abstract: An integrated circuit memory system (33, 17, 18, 21) having memory cells (20) capable of storing multiple bits per memory cell is described. The memory system has a restoring operation in which memory cells' stored charge, which may drift from its initially set condition, is maintained within one of a plurality of predetermined levels corresponding to digital bits of information and defined by a set of special reference voltage values. The memory system (33, 17, 18, 21) has mini-programming and mini-erasing operations to move only the amount of charge into and out of the memory cell sufficient to keep the charge into and out of the predetermined levels. The memory system (33, 17, 18, 21) also has an operation for high speed programming of the memory cells and an erasing operation to narrow the charge distribution of erase memory cells (20) for increasing the spread, and safety margin, between the predetermined levels.

Abstract translation: 描述了具有能够存储每个存储单元多位的存储单元（20）的集成电路存储器系统（33,17,18,21）。 存储器系统具有恢复操作，其中可能从其初始设置状态漂移的存储器单元的存储电荷保持在对应于数字信息位的多个预定电平之一中，并由一组特殊参考电压值 。 存储器系统（33,17,18,21）具有微型编程和微型擦除操作，以将仅电荷量移入和移出存储器单元足以使电荷进入和退出预定级别。 存储器系统（33,17,18,21）还具有用于存储器单元的高速编程的操作和擦除操作，以减小擦除存储器单元（20）的电荷分布，以增加扩展的扩展和安全裕度， 预定水平。

公开(公告)号：WO1997013250A1

公开(公告)日：1997-04-10

申请号：PCT/US1996015924

申请日：1996-10-03

Applicant: AGATE SEMICONDUCTOR, INC.

Inventor： AGATE SEMICONDUCTOR, INC. ,  KHAN, Sakhawat, M.

IPC: G11C11/34

CPC classification number: G11C8/12 ,  G11C8/04 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C19/00 ,  G11C29/00 ,  G11C2211/5624 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5642 ,  G11C2211/5644

Abstract: An integrated circuit storing multiple bits per memory cell is described. The amount of charge stored in a memory cell corresponds to the multiple bits in a memory cell. Dual banks of shift registers (10) are alternately coupled to one or more data pins and to the memory cells of the memory array speed data transfer for reading and writing operation. Reading is performed in the voltage mode to conserve power. During writing operations, reading of a memory cell is performed in the voltage mode to determine whether the desired programming of the memory cell has been achieved. During the reading of a memory cell, the voltage corresponding to the amount of charge stored in a memory cell is compared against a binary search sequence of reference voltages to determine the multiple bits stored in the memory cell.

Abstract translation: 描述了每个存储单元存储多个位的集成电路。 存储单元中存储的电荷量对应于存储单元中的多个位。 两组移位寄存器（10）交替耦合到一个或多个数据引脚和存储器阵列的存储单元，用于读写操作的速度数据传输。 在电压模式下执行读取以节省功率。 在写入操作期间，在电压模式下执行存储单元的读取以确定是否已经实现了存储单元的期望编程。 在存储单元的读取期间，将与存储单元中存储的电荷量相对应的电压与参考电压的二进制搜索序列进行比较，以确定存储在存储单元中的多个位。