公开(公告)号：WO2013040145A1

公开(公告)日：2013-03-21

申请号：PCT/US2012/055044

申请日：2012-09-13

Applicant: SANDISK TECHNOLOGIES, INC. ,  ZHAO, Dengtao ,  LIANG, Guirong ,  DUTTA, Deepanshu

Inventor： ZHAO, Dengtao ,  LIANG, Guirong ,  DUTTA, Deepanshu

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C2211/5644 ,  G11C2211/565

Abstract: A programming technique which reduces program disturb in a non¬ volatile storage system is disclosed. A positive voltage may be applied to a substrate (e.g., p-well) during programming. Biasing the substrate may improve boosting of channels of unselected NAND strings, which may reduce program disturb. The substrate may be charged up during the programming operation, and discharged after programming. Therefore, for operations such as verify and read, the substrate may be grounded. In one embodiment, the substrate is charged just prior to applying a program pulse, then discharged prior to a program verify operation. In one embodiment, the substrate is charged while unselected word lines are ramped up to a pass voltage. The substrate bias may depend on program voltage, temperature, and/or hot count.

Abstract translation: 公开了一种在非易失性存储系统中减少编程干扰的编程技术。 在编程期间可以将正电压施加到衬底（例如，p阱）。 偏置衬底可以提高未选择的NAND串的通道的升高，这可能减少程序干扰。 在编程操作期间可以对衬底进行充电，并在编程之后放电。 因此，对于诸如验证和读取的操作，衬底可以接地。 在一个实施例中，在施加编程脉冲之前对衬底进行充电，然后在程序验证操作之前被放电。 在一个实施例中，在未选择的字线斜坡上升到通过电压的同时对衬底进行充电。 衬底偏置可能取决于程序电压，温度和/或热计数。

公开(公告)号：WO2007078885A3

公开(公告)日：2007-10-11

申请号：PCT/US2006048043

申请日：2006-12-14

Applicant: INTEL CORP ,  TEDROW KERRY D ,  NGUYEN DUNG ,  LI BO ,  HAQUE REZAUL ,  RAHMAN AHSANUR ,  MONASA SAAD P ,  GOLDMAN MATTHEW

Inventor： TEDROW KERRY D ,  NGUYEN DUNG ,  LI BO ,  HAQUE REZAUL ,  RAHMAN AHSANUR ,  MONASA SAAD P ,  GOLDMAN MATTHEW

IPC: G11C11/56 ,  G11C16/08 ,  G11C16/28

CPC classification number: G11C11/5642 ,  G11C7/1048 ,  G11C16/28 ,  G11C2211/5634 ,  G11C2211/5642 ,  G11C2211/5644 ,  G11C2211/5645

Abstract: A multi-level cell memory device performs a read by providing a stepped voltage waveform on a wordline, and comparing cell currents to a substantially constant reference current. Prior to the application of the stepped voltage waveform, the wordline may share charge with another circuit node.

Abstract translation: 多级单元存储器件通过在字线上提供步进电压波形并将单元电流与基本恒定的参考电流进行比较来执行读取。 在施加步进电压波形之前，字线可以与另一电路节点共享电荷。

公开(公告)号：WO1997049086A1

公开(公告)日：1997-12-24

申请号：PCT/US1997007456

申请日：1997-05-05

Applicant: APLUS INTEGRATED CIRCUITS, INC.

Inventor： APLUS INTEGRATED CIRCUITS, INC. ,  LEE, Peter, W. ,  TSAO, Hsing-Ya ,  HSU, Fu-Chang

IPC: G11C11/34

CPC classification number: G11C16/3418 ,  G11C7/1006 ,  G11C7/18 ,  G11C8/00 ,  G11C8/08 ,  G11C8/14 ,  G11C11/56 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0416 ,  G11C16/0491 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3413 ,  G11C16/3431 ,  G11C2211/5644 ,  H01L27/115

Abstract: A flash memory (10) includes a flash transistor array (12a, 12b, 12i), a wordline decoder (14), a bitline decoder (18), a sourceline decoder (22) and a read/write controller (26). The read/write controller (26) has a voltage terminal to receive an input voltage and a data terminal configured to sense a signal on a selected bitline and to generate an internal old amplifier and configured to compare the new data signal to the old data signal and to generate a comparator signal. A voltage generator is configured to selectively apply one of a read set of voltages to program a selected cell and an erase set of voltages to erase a selected cell. In a multistate embodiment, the read/write controller further includes a step counter configured to generate a plurality of step counts. The voltage generator is coupled to the step counter and configured to generate a wordline high voltage (WLHV) signal based on the step count. The WLHV signal is delivered to a selected multistate cell by the wordline decoder to read the contents of the selected multistate cell. Each step compares the old data and the new data in order to determine which memory cells to change. Advantages of the invention include increased flexibility of programming and erasing and improved memory longevity.

Abstract translation: 闪速存储器（10）包括闪存晶体管阵列（12a，12b，12i），字线解码器（14），位线解码器（18），源线解码器（22）和读/写控制器（26）。 读/写控制器（26）具有用于接收输入电压的电压端子和被配置为感测选定位线上的信号并产生内部旧放大器并被配置为将新数据信号与旧数据信号进行比较的数据端 并产生比较器信号。 电压发生器被配置为选择性地施加读取的一组电压以编程所选择的单元和擦除电压组以擦除所选择的单元。 在多状态实施例中，读/写控制器还包括配置成产生多个步数的步数计数器。 电压发生器耦合到步进计数器并且被配置为基于步数产生字线高电压（WLHV）信号。 WLHV信号由字线解码器传送到选定的多状态单元，以读取所选择的多态单元的内容。 每个步骤都比较旧数据和新数据，以确定要更改的存储单元。 本发明的优点包括增加编程和擦除的灵活性并改善记忆寿命。

公开(公告)号：WO1997013250A1

公开(公告)日：1997-04-10

申请号：PCT/US1996015924

申请日：1996-10-03

Applicant: AGATE SEMICONDUCTOR, INC.

Inventor： AGATE SEMICONDUCTOR, INC. ,  KHAN, Sakhawat, M.

IPC: G11C11/34

CPC classification number: G11C8/12 ,  G11C8/04 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C19/00 ,  G11C29/00 ,  G11C2211/5624 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5642 ,  G11C2211/5644

Abstract: An integrated circuit storing multiple bits per memory cell is described. The amount of charge stored in a memory cell corresponds to the multiple bits in a memory cell. Dual banks of shift registers (10) are alternately coupled to one or more data pins and to the memory cells of the memory array speed data transfer for reading and writing operation. Reading is performed in the voltage mode to conserve power. During writing operations, reading of a memory cell is performed in the voltage mode to determine whether the desired programming of the memory cell has been achieved. During the reading of a memory cell, the voltage corresponding to the amount of charge stored in a memory cell is compared against a binary search sequence of reference voltages to determine the multiple bits stored in the memory cell.

Abstract translation: 描述了每个存储单元存储多个位的集成电路。 存储单元中存储的电荷量对应于存储单元中的多个位。 两组移位寄存器（10）交替耦合到一个或多个数据引脚和存储器阵列的存储单元，用于读写操作的速度数据传输。 在电压模式下执行读取以节省功率。 在写入操作期间，在电压模式下执行存储单元的读取以确定是否已经实现了存储单元的期望编程。 在存储单元的读取期间，将与存储单元中存储的电荷量相对应的电压与参考电压的二进制搜索序列进行比较，以确定存储在存储单元中的多个位。

公开(公告)号：WO2013043446A1

公开(公告)日：2013-03-28

申请号：PCT/US2012/055046

申请日：2012-09-13

Applicant: SANDISK TECHNOLOGIES, INC. ,  DUTTA, Deepanshu ,  LEE, Dana ,  LUTZE, Jeffrey

Inventor： DUTTA, Deepanshu ,  LEE, Dana ,  LUTZE, Jeffrey

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/34

CPC classification number: G11C16/04 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3495 ,  G11C2211/5644

Abstract: Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A count of how many of the non-volatile storage elements in the group showed a different result between the reads for the two most recent read levels is determined. The determining is performed on the memory die using the results stored on the memory die. A dynamic read level is determined for distinguishing between a first pair of adjacent data states of the plurality of data states based on the read level when the count reaches a pre-determined criterion. Note that the read level may be dynamically determined on the memory die.

Abstract translation: 本文公开了动态地确定芯片上的读取电平（例如，存储器管芯）。 一种方法包括以第一组读取级别在存储器管芯上读取一组非易失性存储元件。 两个最新的读取电平的结果存储在存储器管芯上。 确定组中有多少非易失性存储元件在两个最新读取级别的读取之间显示不同的结果。 使用存储在存储器管芯上的结果在存储器管芯上进行确定。 当计数达到预定标准时，基于读取级别来确定动态读取级别以区分多个数据状态的第一对相邻数据状态。 注意，读取电平可以在存储器管芯上动态地确定。

公开(公告)号：WO2012099948A1

公开(公告)日：2012-07-26

申请号：PCT/US2012/021701

申请日：2012-01-18

Applicant: MICRON TECHNOLOGY, INC. ,  PEKNY, Theodore, T.

Inventor： PEKNY, Theodore, T.

IPC: G11C7/10 ,  G11C7/06 ,  G11C16/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F12/00 ,  G11C11/5642 ,  G11C16/06 ,  G11C16/26 ,  G11C16/34 ,  G11C27/005 ,  G11C2211/5641 ,  G11C2211/5642 ,  G11C2211/5644

Abstract: The present disclosure includes methods, devices, and systems for outputting data particular quantization of data from memory devices and systems. Outputting data particular quantization of data can include enabling a particular one of a plurality of different quantizations of data. The particular one of the plurality of quantizations of data can then be output.

Abstract translation: 本公开包括用于从存储器设备和系统输出数据特定数据量化的方法，设备和系统。 输出数据的数据的特定量化可以包括启用数据的多个不同量化中的特定的一个。 然后可以输出多个数据量化中的特定一个。

公开(公告)号：WO2009026364A1

公开(公告)日：2009-02-26

申请号：PCT/US2008/073716

申请日：2008-08-20

Applicant: MARVELL WORLD TRADE LTD. ,  SUTARDJA, Pantas

Inventor： SUTARDJA, Pantas

IPC: G11C29/02 ,  G11C11/56 ,  G11C11/26 ,  G11C8/08

CPC classification number: G11C11/5628 ,  G11C7/10 ,  G11C7/1006 ,  G11C7/16 ,  G11C8/08 ,  G11C11/56 ,  G11C16/04 ,  G11C16/06 ,  G11C16/26 ,  G11C16/32 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028 ,  G11C2029/5002 ,  G11C2211/5634 ,  G11C2211/5644

Abstract: The present disclosure relates to reading and calibrating of multilevel programmable threshold transistor arrays. A system includes a voltage generator (106), current sensing amplifiers (22) and a control module (102). The voltage generator outputs a first voltage, which is generated based on received code words, to a first word line that communicates with N transistors (14) each having programmable threshold voltages, where N is an integer greater than 1. The current sensing amplifiers (22) sense currents through the N transistors via N bit lines, respectively, and generate control signals when current through a corresponding one of the N transistors is greater than or equal to a predetermined current. The control module generates measured values of the threshold voltages of the N transistors by compensating the ones of the code words based on at least one of a position of the corresponding ones of the N transistors and a temperature.

Abstract translation: 本公开涉及读取和校准多级可编程阈值晶体管阵列。 系统包括电压发生器（106），电流感测放大器（22）和控制模块（102）。 电压发生器将基于接收到的码字产生的第一电压输出到与具有可编程阈值电压的N个晶体管（14）通信的第一字线，其中N是大于1的整数。电流感测放大器 22）分别通过N个位线检测通过N个晶体管的电流，并且当通过N个晶体管中的相应一个电流的电流大于或等于预定电流时，产生控制信号。 控制模块通过基于N个晶体管的对应位置和温度中的至少一个来补偿所述码字中的一个来产生N个晶体管的阈值电压的测量值。

公开(公告)号：WO01063613A1

公开(公告)日：2001-08-30

申请号：PCT/US2001/003857

申请日：2001-02-06

IPC: G11C11/56 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/10 ,  G11C16/32 ,  G11C2211/5644

Abstract: Method of storing and retrieving multiple bits of information in a multi-level cell (902) of non-volatile memory (900) including programming a plurality of multi-level memory cells (902) within a programming time target. The multi-level memory cells (902) having at least first, second, third and fourth programming levels. The fourth programming level being the erase state, the first programming level being the programming level furthest from the fourth programming level. The second and third programming levels being within the first and fourth programming levels, includes erasing the plurality of multi-level memory cells (902). Then, programming a first group of multi-level memory cells (902) with the first programming level with a first programming pulse count having a first pulse width and a first programming voltage. Then, programming a second group of multi-level memory cells (902) with the second programming level with a second programming pulse count having a second pulse width and a second programming voltage. Then programming a third group of multi-level memory cells (902) with the third programming level with a third programming pulse count having a third pulse width and a third programming voltage.

Abstract translation: 在非易失性存储器（900）的多级单元（902）中存储和检索多位信息的方法，包括在编程时间目标内编程多个多级存储器单元（902）。 具有至少第一，第二，第三和第四编程级别的多级存储器单元（902）。 第四编程电平是擦除状态，第一编程电平是距离第四编程电平最远的编程电平。 第二和第三编程级别在第一和第四编程级别内，包括擦除多个多级存储器单元（902）。 然后，利用具有第一脉冲宽度和第一编程电压的第一编程脉冲计数来编程具有第一编程电平的第一组多电平存储器单元（902）。 然后，利用具有第二脉冲宽度和第二编程电压的第二编程脉冲计数来编程具有第二编程电平的第二组多电平存储器单元（902）。 然后利用具有第三脉冲宽度和第三编程电压的第三编程脉冲计数来编程具有第三编程电平的第三组多电平存储单元（902）。

公开(公告)号：WO1996010256A1

公开(公告)日：1996-04-04

申请号：PCT/US1995012082

申请日：1995-09-22

Applicant: INTEL CORPORATION

Inventor： INTEL CORPORATION ,  FAZIO, Albert ,  ATWOOD, Gregory, E. ,  BAUER, Mark, E.

IPC: G11C07/00

CPC classification number: G11C11/5621 ,  G11C7/16 ,  G11C11/5642 ,  G11C27/005 ,  G11C2211/5634 ,  G11C2211/5642 ,  G11C2211/5644

Abstract: A method and apparatus for sensing the state of floating gate memory cells in a memory array (214). Because of its stability and accuracy, the sensing apparatus (220) may be used for sensing the state of multi-bit floating gate memory cells. The state of memory cell is sensed by applying a variable gate voltage to the top gate of the floating gate memory cell and comparing the cell current to a fixed reference current. A circuit detects when the cell current is equal to the reference current. When the currents are equal, the value of the variable gate voltage indicates the state of the memory cell. For one embodiment, an analog-to-digital converter (210) converts the variable gate voltage to a digital value that is latched when the currents are equal. The latched digital value indicates the state of the memory cell. For this embodiment, a ramp voltage or other suitable variable voltage may be used as the variable gate voltage. For another embodiment, a digital-to-analog converter is used to generate the variable gate voltage.

Abstract translation: 一种用于感测存储器阵列（214）中的浮动栅极存储器单元的状态的方法和装置。 由于其稳定性和精度，感测装置（220）可以用于感测多位浮动栅极存储单元的状态。 通过将可变栅极电压施加到浮动栅极存储器单元的顶部栅极并将单元电流与固定参考电流进行比较来感测存储单元的状态。 电路检测电池电流何时等于参考电流。 当电流相等时，可变栅极电压的值表示存储单元的状态。 对于一个实施例，模数转换器（210）将可变栅极电压转换为当电流相等时被锁存的数字值。 锁存的数字值表示存储单元的状态。 对于该实施例，可以使用斜坡电压或其它合适的可变电压作为可变栅极电压。 对于另一个实施例，使用数模转换器来产生可变栅极电压。

公开(公告)号：WO2016093936A1

公开(公告)日：2016-06-16

申请号：PCT/US2015/054460

申请日：2015-10-07

Applicant: SANDISK TECHNOLOGIES INC.

Inventor： SHUKLA, Pitamber ,  CHIN, Henry ,  LEE, Dana ,  HSU, Cynthia

IPC: G11C11/56 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3431 ,  G11C16/3445 ,  G11C2211/5644

Abstract: A non-volatile memory system mitigates the effects of open block reading by analyzing the un-programmed region of a block before programming to determine a potential for read disturbance. The system may perform partial block erase verification based on a read count value associated with open block reading of the memory block. To mitigate the effects of open block read disturbance, the system performs partial block erase for the un-programmed region of the memory block, and may limit programming in the un-programmed region.

Abstract translation: 非易失性存储器系统通过在编程之前分析块的未编程区域来确定读取干扰的可能性来缓解开放块读取的影响。 该系统可以基于与存储块的开放块读取相关联的读取计数值来执行部分块擦除验证。 为了减轻开放块读取干扰的影响，系统对存储器块的未编程区域执行部分块擦除，并且可能限制未编程区域中的编程。