公开(公告)号：WO2021061413A1

公开(公告)日：2021-04-01

申请号：PCT/US2020/050144

申请日：2020-09-10

Applicant: ALIBABA GROUP HOLDING LIMITED

Inventor： XIANG, Xiaoyan ,  LU, Yimin ,  ZHAO, Chaojun

IPC: G06F9/30

Abstract: An apparatus and a method are disclosed, in the apparatus, a memory management unit includes: a first cache unit, adapted to store a plurality of first source operands and one first write address; a second cache unit, adapted to store at least one pair of a second source operand and a second destination address; a write cache module, adapted to discriminate between destination addresses of a plurality of store instructions, so as to store, in the first cache unit, a plurality of source operands corresponding to consecutive destination addresses, and to store, in the second cache unit, non-consecutive destination addresses and source operands corresponding to the non-consecutive destination addresses, where the first write address is an. initial address of the consecutive destination addresses; and a bus transmission module, adapted to transmit the plurality of first source operands and the first write address in the first cache unit to a. memory through a bus in a write burst transmission mode. In embodiments of the present invention, a burst transmission mode is established between a processor and the bus. This can help reduce occupation of bus address bandwidth and accelerate write efficiency of the memory.

公开(公告)号：WO2021061374A1

公开(公告)日：2021-04-01

申请号：PCT/US2020/049414

申请日：2020-09-04

Applicant: ALIBABA GROUP HOLDING LIMITED

Inventor： XIANG, Xiaoyan ,  ZHU, Taotao ,  ZHU, Feng

IPC: G06F15/163

Abstract: The present invention discloses a multi-core processor and an inter-core data forwarding method. The multi-core processor includes a plurality of processor cores and a multi-core interconnection bus. The multi-core interconnection bus includes: a plurality of request processing interlaces, each of which Is adapted to receive a read data request sent by a coupled processor core, and send the read data request to a request storage unit; and the request storage unit, adapted to receive the read data request sent by the request processing interface, and forward the read data request to another request processing interface, where the request processing interface receives a read data request forwarded by the request storage unit, sends the read data request to the coupled processor core, receives a request result that is returned by the processor core by reading a cache of the processor core, and sends the request result to a request processing interface coupled to a processor core that initiates the request; and receives a request result sent by the another request processing interface, determines valid data based on the received request result, and sends the valid data to the coupled processor core.

公开(公告)号：WO2021061445A1

公开(公告)日：2021-04-01

申请号：PCT/US2020/050847

申请日：2020-09-15

Applicant: ALIBABA GROUP HOLDING LIMITED

Inventor： XIANG, Xiaoyan ,  ZHU, Taotao

IPC: G06F15/163

Abstract: The present invention discloses a multi-core interconnection bus, including a request transceiver module adapted to receive a data request from, a processor core, and forward the data request to a snoop and caching module through a request execution module, where the data request includes a request address; the snoop and caching module adapted to look, up cache data validity information of the request address, acquire data from a shared cache, and sequentially return the cache data validity information and the data, acquired from the shared, cache to the request execution module; and the request execution module adapted to determine, based on the cache data validity information, a target processor core whose local cache stores valid data, forward the data request; to the target processor core, and receive returned data; and determine response data from the data returned by the target processor core and that returned by the snoop and caching module, and return, through the request transceiver module, die response data to the processor core that initiates the data request. The present invention also discloses a corresponding inter-core communication method and a multi-core processor.

公开(公告)号：WO2020198220A1

公开(公告)日：2020-10-01

申请号：PCT/US2020/024451

申请日：2020-03-24

Applicant: ALIBABA GROUP HOLDING LIMITED

Inventor： ZHAO, Chaojun ,  XIANG, Xiaoyan ,  CHEN, Chen ,  ZHU, Taotao

IPC: G06F13/24

Abstract: Embodiments of the present disclosure provide an interrupt controller in a processor, comprising: an interrupt sampling circuitry configured to receive one or more interrupts from one or more interrupt sources that are communicatively coupled to the interrupt controller; and an arbitration circuitry configured to select a to-be-responded interrupt from the received one or more interrupts, the arbitration circuitry comprising: a selection circuitry configured to select from the one or more interrupts a highest-priority interrupt that has a highest priority among the one or more interrupts; and a threshold comparison circuitry communicatively coupled to the selection circuitry, the threshold comparison circuitry configured to compare the priority of the highest-priority interrupt with a preset priority threshold, wherein the arbitration circuitry is configured to select the highest-priority interrupt as the to-be-responded interrupt in response to the threshold comparison circuitry determining that the priority of the highest-priority interrupt is higher than the preset priority threshold.

公开(公告)号：WO2020197971A1

公开(公告)日：2020-10-01

申请号：PCT/US2020/023774

申请日：2020-03-20

Applicant: ALIBABA GROUP HOLDING LIMITED

Inventor： LU, Yimin ,  XIANG, Xiaoyan

IPC: G06F9/38 ,  G06F12/00 ,  G06F9/35 ,  G06F9/24

Abstract: The present disclosure discloses an instruction execution device, a processor including the instruction execution device, a system on chip, and a method for executing a data storage instruction in the processor. The method includes: splitting the data storage instruction into a first split instruction and a second split instruction, wherein the first split instruction is associated with an address operand of the data storage instruction, and the second split instruction is associated with a data operand of the data storage instruction; executing the first split instruction to determine a data storage address corresponding to the address operand; executing the second split instruction to acquire data content corresponding to the data operand; and storing the acquired data content to the determined data storage address in a data storage region. The present disclosure further discloses a corresponding instruction execution device, a processor including the execution device and a system on chip.

公开(公告)号：WO2021061626A1

公开(公告)日：2021-04-01

申请号：PCT/US2020/051966

申请日：2020-09-22

Applicant: ALIBABA GROUP HOLDING LIMITED

Inventor： LU, Yimin ,  XIANG, Xiaoyan

IPC: G06F9/30 ,  G06F9/34 ,  G06F12/06

Abstract: Embodiments of the present disclosure provide methods and apparatuses for an instruction executing method. The method can include: receiving an address-unaligned data load instruction, the data load instruction instructing to read target data from a memory; acquiring a first part of data of the target data from a buffer; acquiring a second part of data of the target data from the memory; and merging the first part of data and the second part of data to obtain the target data.

公开(公告)号：WO2021061446A1

公开(公告)日：2021-04-01

申请号：PCT/US2020/050855

申请日：2020-09-15

Applicant: ALIBABA GROUP HOLDING LIMITED

Inventor： HAO, Ziyi ,  CHEN, Chen ,  XIANG, Xiaoyan ,  ZHU, Feng

IPC: G06F12/10

Abstract: A storage management apparatus, a storage management method, a processor, and a computer system are disclosed. The storage management apparatus includes: at least one translation look-aside buffer, configured to store a plurality of cache entries, where the plurality of cache entries include a plurality of level 1 cache entries and a plurality of level 2 cache entries; and an address translation unit, coupled to the at least one translation look-aside buffer, and adapted to translate, based on one of the plurality of level 1 cache entries, a virtual address specified by a translation request into a corresponding translated address, or when the translation request does not hit any one of the plurality of level.1 cache entries, translate, based on one of the plurality of level 2 cache entries, a virtual address specified by the translation request into a corresponding translated address. In embodiments of the present disclosure, a hierarchical search is performed among the plurality of cache entries based on the virtual address specified by the translation request. Therefore, time required by searching for a cache entry in an address translation process is reduced, efficiency, frequency, and performance of a processor are improved, and power consumption is reduced.

公开(公告)号：WO2021061269A1

公开(公告)日：2021-04-01

申请号：PCT/US2020/043519

申请日：2020-07-24

Applicant: ALIBABA GROUP HOLDING LIMITED

Inventor： LU, Yimin ,  XIANG, Xiaoyan ,  ZHU, Taotao ,  ZHAO, Chaojun

IPC: G06F3/12 ,  G06F12/00 ,  G06F12/06

Abstract: A storage control apparatus, a storage control method a processing apparatus and a computer system are disclosed. The storage control apparatus includes an address detection unit, adapted to detect whether any jump of physical addresses to which sequentially arriving write access request are mapped occurs; and a logic control unit adapted to use a no-write allocate policy if a cache is not hit and no jump of the physical addresses to which the plurality of sequentially arriving write access requests are mapped occurs, where in the no-write allocate policy, if a quantity of continuous jumps of the physical addresses to which the plurality of sequentially arriving write access requests are mapped is less than a preset quantity the logic control unit keeps using the no-write allocate policy, where the preset quantity is greater than 1.

公开(公告)号：WO2021061466A1

公开(公告)日：2021-04-01

申请号：PCT/US2020/051019

申请日：2020-09-16

Applicant: ALIBABA GROUP HOLDING LIMITED

Inventor： HAO, Ziyi ,  XIANG, Xiaoyan ,  ZHU, Feng

IPC: G06F12/10 ,  G06F12/08

Abstract: The present invention discloses a memory management unit, an address translation method, and a processor. The memory management unit includes: a translation lookaside buffer adapted to store a plurality of translation entries, where each, translation entry includes a size flag hit, a virtual address tag, and a physical address tag, the virtual address tag represents a virtual page, the physical address tag represents a physical page corresponding to the virtual page, and the size flag bit. represents a page size of the virtual page: and a translation processing unit adapted to look up a translation entry whose virtual address tag matches a to-he-translated virtual address in the plurality of translation entries based cm the page size represented by the size flag bit of the translation entry, and. translate the virtual address into a physical address based on the matching translation entry.

公开(公告)号：WO2021061465A1

公开(公告)日：2021-04-01

申请号：PCT/US2020/051004

申请日：2020-09-16

Applicant: ALIBABA GROUP HOLDING LIMITED

Inventor： HAO, Ziyi ,  XIANG, Xiaoyan ,  ZHU, Feng

IPC: G06F12/10 ,  G06F12/08

Abstract: A storage management apparatus, a storage management method, a processor, and a computer system are disclosed. The storage management apparatus includes; a translation look-aside buffer configured to store a plurality of cache entries; an address translation unit configured to translate a virtual address specified by a translation request to a corresponding translation address- based on one of the plurality of cache entries; and a control unit coupled to at least one translation look-aside buffer and configured to expand an address range mapped to the selected cache entry. According to embodiments of this disclosure, a translatable address range of the translation look-aside buffer can be expanded, a hit rate of the translation look-aside buffer can be increased, and an execution time of address translation can be reduced, thereby improving performance of the processor and the system.